FXLS90130 datasheet(92/247 Pages) NXP

92 / 247 page

NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

Location

Bit

Address

$62

CH0_SNSDATA0_L

CH0_SNSDATA0[7:0]

$63

CH0_SNSDATA0_H

CH0_SNSDATA0[15:8]

Reset Value

Table 170. Sensor data #0 registers (CHx_SNSDATA0_L, CHx_SNSDATA0_H)

11.2.35 Sensor data #1 registers (CHx_SNSDATA1_L, CHx_SNSDATA1_H)

The sensor data #1 registers are read-only registers which contain the 16-bit sensor

data. The data type for the sensor data #1 registers is selected by the DATATYPE1 bits

in the CHx_CFG_U3 register. See Section 11.2.25.3. See Section 11.6.4.9 for details

regarding the 16-bit sensor data.

These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming

mode. In I2C mode, the SNSDA-TA1_H register value is latched on a read of the

SNSDATA1_L register value until the SNSDATA1_H register is read. To avoid

data mismatch, it is required that the user always read the registers in sequence,

SNSDATA1_L register first, followed by the SNSDATA1_H register.

Location

Bit

Address

$64

CH0_SNSDATA1_L

CH0_SNSDATA1[7:0]

$65

CH0_SNSDATA1_H

CH0_SNSDATA1[15:8]

Reset Value

Table 171. Sensor data #1 registers (CHx_SNSDATA1_L, CHx_SNSDATA1_H)

11.2.36 Channel-specific factory configuration register (CHx_CFG_F)

The channel-specific configuration register is factory programmable OTP register which

contains channel specific configuration information. This register is included in the factory

programmed OTP array error detection.

This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 Programming Mode

when ENDINIT is not set. See Section 11.2.10 for details on the register read process for

this register.

Location

Bit

Address Register

$A0

CH0_

CFG_F

DEV_RANGE[3:0]

RESE

RVED

RESE

RVED

AXIS[1:0]

Table 172. Channel-specific factory configuration register (CHx_CFG_F)

11.2.36.1 Range indication bits (RANGE[3:0])

The range indication bits indicate the full scale range of the channel as shown in

Table 173.

RANGE[3]

RANGE[2]

RANGE[1]

RANGE[0]

Acceleration range

RESERVED

Medium

Table 173. Range indication bits (RANGE[3:0])

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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