FXLS90130 datasheet(67/247 Pages) NXP

67 / 247 page

NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

Initialization phase 2 data

PSI5_INIT2_

D19

D20

Reference

SN4[7:4]

SN4[3:0]

Section 11.2.42, Section 13.4.2.1

USERDATA_6[7:4] USERDATA_E[7:4] Section 11.2.45.1, Section 13.4.2.1

Table 107. PSI5 initialization phase 2 D19 and D20 change bit (PSI5_INIT2_D19)

In DSI3 mode, SPI mode, and I2C mode, the PSI5_INIT2_D19 bit is readable and

writable, but has no impact on device operation or performance.

11.2.16.2 Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])

The oscillator training error counter bits use the number of 4 ms periods used to

determine the error detection time for oscillator training as shown in Table 108. See

Section 11.5.2 for details regarding oscillator training error detection.

OSCTRAIN_ERRCNT[2:0]

4 ms periods counted

before the OSCTRAIN

error flag is set

Minimum time for

error detection

(ms)

256

128

256

Table 108. Oscillator training error counter (OSCTRAIN_ERRCNT[2:0])

11.2.16.3 Capacitor test disable bit (CAPTEST_OFF)

The capacitor test disable bit provides the option to disable the VBUF capacitor test in

DSI3 mode as shown in Table 109.

CAPTEST_OFF Capacitor test status

Capacitor test is operational as specified in Section 11.4.1

Capacitor test will not run

Table 109. Capacitor test disable bit (CAPTEST_OFF)

If a capacitor error is present, the VBUFUV_ERR bit is set in the DEVSTAT1 register as

specified in Section 11.4.1. The presence of the VBUFUV_ERR will prevent the user from

writing to the TIMING_CFG2 register to disable the capacitor test unless and until the

capacitor error recovers.

In SPI and I2C mode, the CAPTEST_OFF bit is readable and writable, but has no impact

on device operation or performance.

In PSI5 mode, the CAPTEST_OFF bit is readable and writable, but has no impact on

device operation or performance.

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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