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FXLS90130 Datasheet(PDF) 53 Page - NXP Semiconductors |
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FXLS90130 Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 247 page  NXP Semiconductors FXLS9xxx0 Single channel inertial sensor 11.2.7.2 Write OTP enable and programming bits Register writes executed by the user to the user programmed OTP array only update the mirror register contents for the OTP array, not the actual OTP registers. To copy the values to the actual OTP registers, a write must be executed to the WRITE_OTP_EN register with the UOTP_WR_INIT bit set. The state of the UOTP_REGION[1:0], the EX_COMMTYPE, and the EX_PADDR bits in the command determine which region of OTP are written as shown in Table 77. EX_ COMMTYPE EX_PADDR UOTP_ REGION[1] UOTP_ REGION[0] OTP write operation Special conditions x x 0 0 Write the current contents of the UF0 registers to OTP x x 0 1 Write the current contents of the UF1 registers to OTP 0 0 1 0 Write the current contents of the UF2 registers to OTP, including the COMMTYPE register and the PHYSADDR register 0 1 1 0 Write the current contents of the UF2 registers to OTP, including COMMTYPE and excluding PHYSADDR. PHYSADDR = 0x00 after OTP Write 1 0 1 0 Write the current contents of the UF2 registers to OTP, excluding COMMTYPE and including PHYSADDR. User must not overwrite COMMTYPE 1 1 1 0 Write the current contents of the UF2 registers to OTP, excluding COMMTYPE and excluding PHYSADDR. User must not overwrite COMMTYPE PHYSADDR = 0x00 after OTP Write x x 1 1 Reserved for Future Use Table 77. Write OTP enable and programming bits The UF0 and UF1 user OTP regions as well as the NXP programmed F OTP regions share common mirror registers. For this reason, writes to the OTP for each region must be completed independently according to the procedure below. Depending upon the operating mode used, the user needs to write the UF2 values to OTP either with or without the PHYSADDR register and the COMMTYPE register being written. If Discovery Mode or switch connected daisy chain mode is used, the PHYSADDR register must remain un-programmed (0x0000). If a pre-programmed bus mode is used, the PHYSADDR register must be programmed to a non-zero value. To support these two user modes, the EX_PADDR bit is used as described in Table 77. Once a region is written using the OTP Write sequence, the LOCK_Uxx bit in the appropriate CRC_xxx register is automatically set, locking the array from future writes. Once a region is locked, an error detection is activated to detect changes to the register values. Register values in the UF2 region can be over-written using register write commands, but no new values can be written to the OTP. The procedure for writing to the user OTP array UF0 and UF1 regions is: 1. Read the appropriate CRC_UFx register and confirm the LOCK_Uxx bit is not set. FXLS9xxx0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 53 / 247 |
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