FXLS90130 datasheet(89/247 Pages) NXP

89 / 247 page

NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

Location

Bit

Address

$50

OC_PHASE_CFG CH0_OCFINAL

RESERVED

Unprogrammed OTP Value

Table 162. Offset cancellation user configuration register (OC_PHASE_CFG)

11.2.30.1 Channel 0 offset cancellation final phase control bit (CH0_OCFINAL)

The channel 0 offset cancellation final phase control bit provides the option for the user to

control the final offset cancellation phase for normal mode as shown in Table 163.

CH0_

OCFINAL

Channel 0 offset cancellation final phase for normal mode

Phase 6 (a or b) as specified in the table in Section 11.6.4.6

Phase 5 as specified in the table in Section 11.6.4.6

(Rate Limiting is always bypassed)

Table 163. Channel 0 offset cancellation final phase control bit (CH0_OCFINAL)

11.2.31 User offset calibration registers (Chx_U_OFFSET_L, Chx_U_OFFSET_H)

The user offset calibration registers contain a user programmable 16-bit signed offset

correction value for the sensor data.

These registers can be written during initialization but are locked once the ENDINIT bit

is set. Refer to Section 11.2.6. The registers are included in the read/write array error

detection.

Location

Bit

Address

$55

CH0_U_OFFSET_L

CH0_U_OFFSET[7:0]

$56

CH0_U_OFFSET_H

CH0_U_OFFSET[15:8]

Unprogrammed OTP Value

Table 164. User offset calibration registers (Chx_U_OFFSET_L, Chx_U_OFFSET_H)

The value programmed into the user offset calibration register is directly added to the

sensor data after the user sensitivity scaling but before the offset cancellation. See

Section 11.6.4.9 for scaling of the CHx_U_OFFSET value. The CHx-_U_OFFSET

LSB change in the CHx-_U_OFFSET register will result in a 1 LSB change to the value in

the SNSDATAx registers.

Note: The user offset calibration register range is larger than the full scale range of the

output. The user must take care to ensure that the value stored in this register does not

result in a compressed output range or a railed output.

11.2.32 Channel-specific status register (CH0_STAT)

The channel-specific status register is a read-only register which contains sensor data-

specific status information.

This register is readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming mode.

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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