LTM2987 datasheet(23/114 Pages) AD

23 / 114 page

LTC2971

Rev. 0

For more information www.analog.com

OPERATION

VDDIO

The VDDIO pin defines the input threshold of the SDA, SCL,

ALERTB, PWRGD, FAULTB[1:0], CONTROL[1:0], PG[1:0],

WDI/RESETB,andWPpinstoallowforlowervoltagedigital

communication.AninternalresistivedividerattheVDDIOpin

sets the internal threshold voltage to approximately 45%

of the VDDIO pin voltage. The VOUT_EN[1:0], AUXFAULTB,

and SHARE_CLK pins are not affected by the voltage at

the VDDIO pin and should always be pulled up to VDD33.

PMBus SERIAL DIGITAL INTERFACE

TheLTC2971communicateswithahost(master)usingthe

standard PMBus serial bus interface. The PMBus Timing

Diagram shows the timing relationship of the signals on

the bus. The two bus lines, SDA and SCL, must be high

when the bus is not in use. External pull-up resistors or

current sources are required on these lines.

The LTC2971 is a slave device. The master can com-

municate with the LTC2971 using the following formats:

• Master transmitter, slave receiver

• Master receiver, slave transmitter

The following SMBus commands are supported:

• Write Byte, Write Word, Send Byte

• Read Byte, Read Word, Block Read

• Alert Response Address

Figures 1 to 13 illustrate the aforementioned SMBus pro-

tocols. All transactions support PEC (packet error check)

and GCP (group command protocol). The Block Read

supports 255 bytes of returned data. For this reason, the

SMBus timeout may be extended using the Mfr_config_

all_longer_pmbus_timeout setting.

PMBus

PMBus is an industry standard that defines a means

of communication with power conversion devices. It is

comprised of an industry standard SMBus serial interface

and the PMBus command language.

The PMBus two wire interface is an incremental extension

of the SMBus. SMBus is built upon I2C with some minor

differences in timing, DC parameters and protocol. The

SMBus protocols are more robust than simple I2C byte

commands because they provide timeouts to prevent

bus hangs and optional Packet Error Checking (PEC) to

ensure data integrity. In general, a master device that

can be configured for I2C communication can be used

for PMBus communication with little or no change to

hardware or firmware.

For a description of the minor extensions and exceptions

PMBusmakestoSMBus,refertoPMBusSpecificationPart

1 Revision 1.1: Section 5: Transport. This can be found at:

www.pmbus.org

ForadescriptionofthedifferencesbetweenSMBusandI2C,

refer to System Management Bus (SMBus) Specification

Version 2.0: Appendix B – Differences between SMBus

and I2C. This can be found at:

www.smbus.org

WhenusinganI2CcontrollertocommunicatewithaPMBus

part it is important that the controller be able to write a

byte of data without generating a stop. This will allow the

controller to properly form the repeated start of a PMBus

read command by concatenating a start command byte

write with an I2C read.

Device Address

The I2C/SMBus address of the LTC2971 equals the base

address + N where N is a number from 0 to 8. N can be

configured by setting the ASEL0 and ASEL1 pins to VDD33,

GND or FLOAT. See Table 1. Using one base address and

the nine values of N, nine LTC2971s can be connected

together to control eighteen outputs. The base address is

storedintheMFR_I2C_BASE_ADDRESSregister.Thebase

address can be written to any value, but generally should

not be changed unless the desired range of addresses

overlap existing addresses. Ensure that the address range

does not overlap with other I2C/SMBus device or global

addresses, including I2C/SMBus multiplexers and bus

buffers. This will bring you great happiness.

TheLTC2971alwaysrespondstoitsglobaladdressandthe

SMBus Alert Response address regardless of the state of

itsASELpinsandtheMFR_I2C_BASE_ADDRESSregister.

LTM2987 Datasheet(PDF) 23 Page - Analog Devices

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