AT91 datasheet(59/153 Pages) ATMEL

59 / 153 page

AT91X40 Series

1354D–ATARM–08/02

Interrupt Clearing and

Setting

All interrupt sources which are programmed to be edge triggered (including FIQ) can be

individually set or cleared by respectively writing to the registers AIC_ISCR and

AIC_ICCR. This function of the interrupt controller is available for auto-test or software

debug purposes.

Fast Interrupt Request

The external FIQ line is the only source which can raise a fast interrupt request to the

processor. Therefore, it has no priority controller.

The external FIQ line can be programmed to be positive or negative edge triggered or

high- or low-level sensitive in the AIC_SMR0 register.

The fast interrupt handler address can be stored in the AIC_SVR0 register. The value

written into this register is available by reading the AIC_FVR register when an FIQ inter-

rupt is raised. By storing the following instruction at address 0x0000001C, the processor

will load the program counter with the interrupt handler address stored in the AIC_FVR

ldr PC,[PC,# -&F20]

Alternatively the interrupt handler can be stored starting from address 0x0000001C as

described in the ARM7TDMI datasheet.

Software Interrupt

Interrupt source 1 of the advanced interrupt controller is a software interrupt. It must be

programmed to be edge triggered in order to set or clear it by writing to the AIC_ISCR

and AIC_ICCR.

This is totally independent of the SWI instruction of the ARM7TDMI processor.

Spurious Interrupt

When the AIC asserts the NIRQ line, the ARM7TDMI enters IRQ Mode and the interrupt

handler reads the IVR. It may happen that the AIC de-asserts the NIRQ line after the

core has taken into account the NIRQ assertion and before the read of the IVR.

This behavior is called a Spurious Interrupt.

The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector

when the IVR is read. The Spurious Vector can be programmed by the user when the

vector table is initialized.

A spurious interrupt may occur in the following cases:

•

With any sources programmed to be level sensitive, if the interrupt signal of the AIC

input is de-asserted at the same time as it is taken into account by the ARM7TDMI.

•

If an interrupt is asserted at the same time as the software is disabling the

corresponding source through AIC_IDCR (this can happen due to the pipelining of

the ARM core).

The same mechanism of spurious interrupt occurs if the ARM7TDMI reads the IVR

(application software or ICE) when there is no interrupt pending. This mechanism is also

valid for the FIQ interrupts.

Once the AIC enters the spurious interrupt management, it asserts neither the NIRQ nor

the NFIQ lines to the ARM7TDMI as long as the spurious interrupt is not acknowledged.

Therefore, it is mandatory for the Spurious Interrupt Service Routine to acknowledge the

“spurious” behavior by writing to the AIC_EOICR (End of Interrupt) before returning to

the interrupted software. It also can perform other operation(s), e.g., trace possible

undesirable behavior.

AT91 Datasheet(PDF) 59 Page - ATMEL Corporation

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