AT91 datasheet(74/153 Pages) ATMEL

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AT91X40 Series

1354D–ATARM–08/02

PIO: Parallel I/O

Controller

The AT91X40 Series has 32 programmable I/O lines. Six pins are dedicated as general

purpose I/O pins (P16, P17, P18, P19, P23 and P24). Other I/O lines are multiplexed

with an external signal of a peripheral to optimize the use of available package pins (see

Table 10). The PIO controller also provides an internal interrupt signal to the Advanced

Interrupt Controller.

Multiplexed I/O Lines

Some I/O lines are multiplexed with an I/O signal of a peripheral. After reset, the pin is

generally controlled by the PIO Controller and is in Input Mode. Table 10 indicates which

of these pins are not controlled by the PIO Controller after reset.

When a peripheral signal is not used in an application, the corresponding pin can be

used as a parallel I/O. Each parallel I/O line is bi-directional, whether the peripheral

defines the signal as input or output. Figure 34 shows the multiplexing of the peripheral

signals with Parallel I/O signals.

If a pin is multiplexed between the PIO Controller and a peripheral, the pin is controlled

by the registers PIO_PER (PIO Enable) and PIO_PDR (PIO Disable). The register

PIO_PSR (PIO Status) indicates whether the pin is controlled by the corresponding

peripheral or by the PIO Controller.

If a pin is a general-purpose parallel I/O pin (not multiplexed with a peripheral),

PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the bits correspond-

ing to these pins.

When the PIO is selected, the peripheral input line is connected to zero.

Output Selection

The user can enable each individual I/O signal as an output with the registers PIO_OER

(Output Enable) and PIO_ODR (Output Disable). The output status of the I/O signals

can be read in the register PIO_OSR (Output Status). The direction defined has effect

only if the pin is configured to be controlled by the PIO Controller.

I/O Levels

Each pin can be configured to be driven high or low. The level is defined in four different

ways, according to the following conditions.

If a pin is controlled by the PIO Controller and is defined as an output (see “Output

Selection” above), the level is programmed using the registers PIO_SODR (Set Output

Data) and PIO_CODR (Clear Output Data). In this case, the programmed value can be

read in PIO_ODSR (Output Data Status).

If a pin is controlled by the PIO Controller and is not defined as an output, the level is

determined by the external circuit.

If a pin is not controlled by the PIO Controller, the state of the pin is defined by the

peripheral (see peripheral datasheets).

In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data

Status).

Filters

Optional input glitch filtering is available on each pin of the AT91M40800, the

AT91M40807 and the AT91R40807. Filtering is controlled by the registers PIO_IFER

(Input Filter Enable) and PIO_IFDR (Input Filter Disable). The input glitch filtering can be

selected whether the pin is used for its peripheral function or as a parallel I/O line. The

each pin.

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