AT91 datasheet(11/153 Pages) ATMEL

11 / 153 page

AT91X40 Series

1354D–ATARM–08/02

No abort is generated when reading the internal memory or by accessing the internal

peripheral, whether the address is defined or not.

When a write-protected area is accessed, the memory controller detects it and gener-

ates an abort but does not cancel the access.

External Bus Interface

The External Bus Interface handles the accesses between addresses 0x0040 0000 and

0xFFC0 0000. It generates the signals that control access to the external devices, and

can be configured from eight 1M byte banks up to four 16M bytes banks. It supports

byte, half-word and word aligned accesses.

For each of these banks, the user can program:

•

Number of wait states

•

Number of data float times (wait time after the access is finished to prevent any bus

contention in case the device is too long in releasing the bus)

•

Data bus width (8-bit or 16-bit)

•

With a 16-bit wide data bus, the user can program the EBI to control one 16-bit

device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-

bit memory (Byte Write Access Mode).

The External Bus Interface features also the Early Read Protocol, configurable for all the

devices, that significantly reduces access time requirements on an external device in

the case of single clock cycle access.

Peripherals

The AT91X40 Series’ peripherals are connected to the 32-bit wide Advanced Peripheral

Bus. Peripheral registers are only word accessible – byte and half-word accesses are

not supported. If a byte or a half-word access is attempted, the memory controller auto-

matically masks the lowest address bits and generates a word access.

Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte

address space).

Peripheral Registers

The following registers are common to all peripherals:

•

Control Register – write only register that triggers a command when a one is written

to the corresponding position at the appropriate address. Writing a zero has no

effect.

•

Mode Register – read/write register that defines the configuration of the peripheral.

Usually has a value of 0x0 after a reset.

•

Data Registers – read and/or write register that enables the exchange of data

between the processor and the peripheral.

•

Status Register – read only register that returns the status of the peripheral.

•

Enable/Disable/Status Registers are shadow command registers. Writing a one in

the Enable Register sets the corresponding bit in the Status Register. Writing a one

in the Disable Register resets the corresponding bit and the result can be read in the

Status Register. Writing a bit to zero has no effect. This register access method

maximizes the efficiency of bit manipulation, and enables modification of a register

with a single non-interruptible instruction, replacing the costly read-modify-write

operation.

Unused bits in the peripheral registers are shown as “–“ and must be written at 0 for

upward compatibility. These bits read 0.

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