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AT91 Datasheet(PDF) 75 Page - ATMEL Corporation |
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AT91 Datasheet(HTML) 75 Page - ATMEL Corporation |
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75 / 153 page  75 AT91X40 Series 1354D–ATARM–08/02 Interrupts Each parallel I/O can be programmed to generate an interrupt when a level change occurs. This is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Dis- able) registers which enable/disable the I/O interrupt by setting/clearing the corresponding bit in the PIO_IMR. When a change in level occurs, the corresponding bit in the PIO_ISR (Interrupt Status) is set whether the pin is used as a PIO or a peripheral and whether it is defined as input or output. If the corresponding interrupt in PIO_IMR (Interrupt Mask) is enabled, the PIO interrupt is asserted. When PIO_ISR is read, the register is automatically cleared. User Interface Each individual I/O is associated with a bit position in the Parallel I/O user interface reg- isters. Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. |
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