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AT91 Datasheet(PDF) 99 Page - ATMEL Corporation |
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AT91 Datasheet(HTML) 99 Page - ATMEL Corporation |
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99 / 153 page ![]() 99 AT91X40 Series 1354D–ATARM–08/02 USART: Universal Synchronous/ Asynchronous Receiver/ Transmitter The AT91X40 Series provides two identical, full-duplex, universal synchronous/asyn- chronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: • Programmable Baud Rate Generator • Parity, Framing and Overrun Error Detection • Line Break Generation and Detection • Automatic Echo, Local Loopback and Remote Loopback channel modes • Multi-drop Mode: Address Detection and Generation • Interrupt Generation • Two Dedicated Peripheral Data Controller channels • 5-, 6-, 7-, 8- and 9-bit character length Figure 36. USART Block Diagram Pin Description Each USART channel has the following external signals: Notes: 1. After a hardware reset, the USART pins are not enabled by default (see “PIO: Parallel I/O Controller” on page 74). The user must configure the PIO Controller before enabling the transmitter or receiver. 2. If the user selects one of the internal clocks, SCK can be configured as a PIO. Peripheral Data Controller Receiver Channel Transmitter Channel Control Logic Interrupt Control Baud Rate Generator Receiver Transmitter AMBA ASB APB USxIRQ MCK MCK/8 RXD TXD SCK USART Channel Baud Rate Clock PIO: Parallel I/O Controller Name Description SCK USART Serial clock can be configured as input or output: SCK is configured as input if an External clock is selected (USCLKS[1] = 1) SCK is driven as output if the External Clock is disabled (USCLKS[1] = 0) and Clock output is enabled (CLKO = 1) TXD Transmit Serial Data is an output RXD Receive Serial Data is an input |
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