AT91 datasheet(102/153 Pages) ATMEL

102 / 153 page

102

AT91X40 Series

1354D–ATARM–08/02

Synchronous Receiver

When configured for synchronous operation (SYNC = 1), the receiver samples the RXD

signal on each rising edge of the Baud Rate clock. If a low level is detected, it is consid-

ered as a start. Data bits, parity bit and stop bit are sampled and the receiver waits for

the next start bit. See example in Figure 40.

Figure 40. Synchronous Mode: Character Reception

Receiver Ready

When a complete character is received, it is transferred to the US_RHR and the RXRDY

status bit in US_CSR is set. If US_RHR has not been read since the last transfer, the

OVRE status bit in US_CSR is set.

Parity Error

Each time a character is received, the receiver calculates the parity of the received data

bits, in accordance with the field PAR in US_MR. It then compares the result with the

received parity bit. If different, the parity error bit PARE in US_CSR is set.

Framing Error

If a character is received with a stop bit at low level and with at least one data bit at high

level, a framing error is generated. This sets FRAME in US_CSR.

Time-out

This function allows an idle condition on the RXD line to be detected. The maximum

delay for which the USART should wait for a new character to arrive while the RXD line

is inactive (high level) is programmed in US_RTOR (Receiver Time-out). When this reg-

ister is set to 0, no time-out is detected. Otherwise, the receiver waits for a first character

and then initializes a counter which is decremented at each bit period and reloaded at

each byte reception. When the counter reaches 0, the TIMEOUT bit in US_CSR is set.

The user can restart the wait for a first character with the STTTO (Start Time-out) bit in

US_CR.

Calculation of time-out duration:

RXD

True Start Detection

Sampling

Parity Bit

Stop Bit

Example: 8-bit, parity enabled 1 stop

SCK

Duration

= Value x

Bit period

AT91 Datasheet(PDF) 102 Page - ATMEL Corporation