AT91 datasheet(105/153 Pages) ATMEL

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105

AT91X40 Series

1354D–ATARM–08/02

Each of these steps can be scheduled by using the interrupt if the bit TXRDY in US_IMR

is set. For character transmission, the USART channel must be enabled before sending

a break.

Receive Break

The receiver detects a break condition when all data, parity and stop bits are low. When

the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. An end of

receive break is detected by a high level for at least 2/16 of a bit period in Asynchronous

Mode or at least one sample in Synchronous Mode. RXBRK is also asserted when an

end of break is detected.

Both the beginning and the end of a break can be detected by interrupt if the bit

US_IMR.RXBRK is set.

Peripheral Data

Controller

Each USART channel is closely connected to a corresponding Peripheral Data Control-

ler channel. One is dedicated to the receiver. The other is dedicated to the transmitter.

Note:

The PDC is disabled if 9-bit character length is selected (MODE9 = 1) in US_MR.

The PDC channel is programmed using US_TPR (Transmit Pointer) and US_TCR

(Transmit Counter) for the transmitter and US_RPR (Receive Pointer) and US_RCR

(Receive Counter) for the receiver. The status of the PDC is given in US_CSR by the

ENDTX bit for the transmitter and by the ENDRX bit for the receiver.

The pointer registers (US_TPR and US_RPR) are used to store the address of the

transmit or receive buffers. The counter registers (US_TCR and US_RCR) are used to

store the size of these buffers.

The receiver data transfer is triggered by the RXRDY bit and the transmitter data trans-

fer is triggered by TXRDY. When a transfer is performed, the counter is decremented

and the pointer is incremented. When the counter reaches 0, the status bit is set

(ENDRX for the receiver, ENDTX for the transmitter in US_CSR) which can be pro-

grammed to generate an interrupt. Transfers are then disabled until a new non-zero

counter value is programmed.

Interrupt Generation

Each status bit in US_CSR has a corresponding bit in US_IER (Interrupt Enable) and

US_IDR (Interrupt Disable) which controls the generation of interrupts by asserting the

USART interrupt line connected to the Advanced Interrupt Controller. US_IMR (Interrupt

Mask Register) indicates the status of the corresponding bits.

When a bit is set in US_CSR and the same bit is set in US_IMR, the interrupt line is

asserted.

Channel Modes

The USART can be programmed to operate in three different test modes, using the field

CHMODE in US_MR.

Automatic Echo Mode allows bit by bit re-transmission. When a bit is received on the

RXD line, it is sent to the TXD line. Programming the transmitter has no effect.

Local Loopback Mode allows the transmitted characters to be received. TXD and RXD

pins are not used and the output of the transmitter is internally connected to the input of

the receiver. The RXD pin level has no effect and the TXD pin is held high, as in idle

state.

Remote Loopback Mode directly connects the RXD pin to the TXD pin. The Transmitter

and the Receiver are disabled and have no effect. This mode allows bit by bit re-

transmission.

AT91 Datasheet(PDF) 105 Page - ATMEL Corporation

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