AT91 datasheet(78/153 Pages) ATMEL

78 / 153 page

AT91X40 Series

1354D–ATARM–08/02

PIO User Interface

PIO Base Address:

0xFFFF0000 (Code Label PIO_BASE)

Notes:

1. The reset value of this register depends on the level of the external pins at reset.

2. This register is cleared at reset. However, the first read of the register can give a value not equal to zero if any changes have

occurred on any pins between the reset and the read.

3. This register exists in the AT91R40008 but its value has no meaning, since the filters are not implemented.

Table 11. PIO Controller Memory Map

Offset

Name

Access

Reset State

0x00

PIO Enable Register

PIO_PER

Write Only

–

0x04

PIO Disable Register

PIO_PDR

Write Only

–

0x08

PIO Status Register

PIO_PSR

Read Only

0x01FFFFFF

(see also Table

10)

0x0C

Reserved

–

0x10

Output Enable Register

PIO_OER

Write Only

–

0x14

Output Disable Register

PIO_ODR

Write Only

–

0x18

Output Status Register

PIO_OSR

Read Only

0x1C

Reserved

–

0x20

Input Filter Enable Register

PIO_IFER

Write Only

–

0x24

Input Filter Disable Register

PIO_IFDR

Write Only

–

0x28

Input Filter Status Register(3)

PIO_IFSR

Read Only

0x2C

Reserved

–

0x30

Set Output Data Register

PIO_SODR

Write Only

–

0x34

Clear Output Data Register

PIO_CODR

Write Only

–

0x38

Output Data Status Register

PIO_ODSR

Read Only

0x3C

Pin Data Status Register

PIO_PDSR

Read Only

(see Note 1)

0x40

Interrupt Enable Register

PIO_IER

Write Only

–

0x44

Interrupt Disable Register

PIO_IDR

Write Only

–

0x48

Interrupt Mask Register

PIO_IMR

Read Only

0x4C

Interrupt Status Register

PIO_ISR

Read Only

(see Note 2)

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