AT91 datasheet(30/153 Pages) ATMEL

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AT91X40 Series

1354D–ATARM–08/02

Figure 18. One Wait State Access

Notes:

1. Early Read Protocol

2. Standard Read Protocol

Data Float Wait State

Some memory devices are slow to release the external bus. For such devices it is nec-

essary to add wait states (data float waits) after a read access before starting a write

access or a read access to a different external memory.

The Data Float Output Time (tDF) for each external memory device is programmed in the

TDF field of the EBI_CSR register for the corresponding chip select. The value (0 - 7

clock cycles) indicates the number of data float waits to be inserted and represents the

time allowed for the data output to go high impedance after the memory is disabled.

Data float wait states do not delay internal memory accesses. Hence, a single access to

an external memory with long tDF will not slow down the execution of a program from

internal memory.

The EBI keeps track of the programmed external data float time during internal

accesses, to ensure that the external memory system is not accessed while it is still

busy.

Internal memory accesses and consecutive accesses to the same external memory do

not have added Data Float wait states.

ADDR

NCS

NWE

MCK

1 Wait State Access

NRD

(1)

(2)

AT91 Datasheet(PDF) 30 Page - ATMEL Corporation