AT91 datasheet(8/153 Pages) ATMEL

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AT91X40 Series

1354D–ATARM–08/02

Product Overview

Power Supply

The AT91x40 Series Microcontrollers have two types of power supply pins - VDDIO and

VDDCORE. However, the AT91M40800, the AT91M40807 and the AT91R40807 have

single-supply VDD, VDDIO and VDDCORE pins that have to be tied to the same volt-

age. For further details on power supplies and acceptable voltage range on VDD,

VDDIO and VDDCORE, refer to the product Summary Datasheet or the product Electri-

cal Characteristics datasheet.

Input/Output

Considerations

The AT91M40807, the AT91R40807 and the AT91R40008 accept voltage levels up to

their power supply limit on the pads.

The AT91M40800 Microcontroller I/O pads are 5V-tolerant, enabling it to interface with

external 5V devices without any additional components. 5V-tolerant means that the

AT91M40800 accepts 5V (3V) on the inputs even if it is powered at 3V (2V). Refer to the

AT91M40800 Electrical Characteristics datasheet for further details.

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maxi-

mum flexibility. It is recommended that in any application phase, the inputs to the

AT91X40 Series Microcontroller be held at valid logic levels to minimize the power

consumption.

Master Clock

The AT91X40 Series Microcontrollers have a fully static design and work on the Master

Clock (MCK), provided on the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the pin MCKO, which is

multiplexed with a general-purpose I/O line. While NRST is active, the MCKO stays low.

After the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO

Controller must be programmed to use this pin as standard I/O line.

Reset

Reset restores the default states of the user interface registers (defined in the user inter-

face of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch

from address zero. Except for the program counter the ARM7TDMI registers do not

have defined reset states.

NRST Pin

NRST is active low-level input. It is asserted asynchronously, but exit from reset is syn-

chronized internally to the MCK. The signal presented on MCK must be active within the

specification for a minimum of 10 clock cycles up to the rising edge of NRST, to ensure

correct operation. The first processor fetch occurs 80 clock cycles after the rising edge

of NRST.

Watchdog Reset

The watchdog can be programmed to generate an internal reset. In this case, the reset

has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not

sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted

and the watchdog triggers the internal reset, the NRST pin has priority.

Emulation Function

Tri-state Mode

The AT91X40 Series provides a tri-state mode, which is used for debug purposes. This

enables the connection of an emulator probe to an application board without having to

desolder the device from the target board. In tri-state mode, all the output pin drivers of

the AT91X40 Series Microcontroller are disabled.

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