FS4500 datasheet(43/153 Pages) NXP

43 / 153 page

NXP Semiconductors

FS6500-FS4500-ASILD

Safety power system basis chip with CAN FD and LIN transceivers

• The new WD window duration (except after disable) is taken into account when a write in the WD_ANSWER

(WD timeout).

• The new WD window duration after disable is taken into account when the SPI command is validated.

The duty cycle of the window is set to 50 % ±10 % and is not modifiable.

FS CLK

accuracy

window period

CLOSED

OPEN

refresh

slot

CLOSED

OPEN

refresh

slot

FS CLK

accuracy

aaa-037748

Figure 19. Windowed watchdog with FS clock accuracy

12.5.2.3 Watchdog in debug mode

When the device is in debug mode (entered via the DEBUG pin), the watchdog continues to operate, but does

not affect the device operation by asserting a reset of the fail-safe pins. For the user, operation appears without

the watchdog. If needed and to debug the watchdog itself, the user can operate as in normal mode and check

LFSR values, the watchdog refresh counter, the watchdog error counter, and the reset counter. This allows the

user to debug their software and ensure a good watchdog strategy in the application.

12.5.2.4 Wrong watchdog refresh handling

Error counters and strategy are implemented in the device to manage wrong watchdog refreshes from the MCU.

According to consecutive numbers of wrong watchdog refreshes, the device can decide to assert the RSTB

and/or FS0B pin, depending on the safety configuration set during the INIT_FS phase (WD_IMPACT bit in

INIT_SF_IMPACT register, Table 86).

12.5.2.5 Watchdog error counter

The watchdog error counter is implemented in the device to filter the incorrect watchdog refresh. Each time a

watchdog failure occurs, the device increments this counter by 2. The WD error counter is decremented by 1

each time the watchdog is properly refreshed. This principle ensures a cyclic ’OK/NOK’ behavior converges to

a failure detection. To allow flexibility in the application, the maximum value of this counter is configurable in the

INIT_WD_CNT register, but only when device is in INIT_FS mode.

FS6500-FS4500-ASILD

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 8 — 5 August 2024

Document feedback

43 / 153

FS4500 Datasheet(PDF) 43 Page - NXP Semiconductors

FS4500 Datasheet(HTML) 43 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL