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FS4500 Datasheet(PDF) 93 Page - NXP Semiconductors |
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FS4500 Datasheet(HTML) 93 Page - NXP Semiconductors |
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93 / 153 page  NXP Semiconductors FS6500-FS4500-ASILD Safety power system basis chip with CAN FD and LIN transceivers 13.3.5 INIT_INH_INT Write bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 1 0 0 0 1 0 1 P 0 0 0 INT_INH_ 5 INT_INH_ 4 INT_INH_ 3 INT_INH_ 2 INT_INH_ 0 MISO SPI_G WU_G CAN_G LIN_G IO_G VPRE _G VCORE _G VOTHERS_ G RES ERVED RES ERVED RES ERVED INT_INH_ 5 INT_INH_ 4 INT_INH_ 3 INT_INH_ 2 INT_INH_ 0 Table 30. INIT_INH_INT register description Read bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 MOSI 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 MISO SPI_G WU_G CAN_G LIN_G IO_G VPRE _G VCORE _G VOTHERS_ G RES ERVED RES ERVED RES ERVED INT_INH_ 5 INT_INH_ 4 INT_INH_ 3 INT_INH_ 2 INT_INH_ 0 Description Inhibit the interrupt pulse for IO_5 (masked in IO_G) 0 INT not masked 1 INT masked INT_INH_5 Reset condition Power on reset Description Inhibit the interrupt pulse for IO_4 (masked in IO_G) 0 INT not masked 1 INT masked INT_INH_4 Reset condition Power on reset Description Inhibit the interrupt pulse for IO_3 (masked in IO_G) 0 INT not masked 1 INT masked INT_INH_3 Reset condition Power on reset Description Inhibit the interrupt pulse for IO_2 (masked in IO_G) 0 INT not masked 1 INT masked INT_INH_2 Reset condition Power on reset Description Inhibit the interrupt pulse for IO_0 (masked in IO_G) 0 INT not masked 1 INT masked INT_INH_0 Reset condition Power on reset Table 31. INIT IO_WU2 description and configuration of the bits (default value in bold) FS6500-FS4500-ASILD All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 8 — 5 August 2024 Document feedback 93 / 153 |
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