PM3350-SW datasheet(111/224 Pages) PMC

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ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

109

into the appropriate transmit queue(s). Note that entry into multiple queues - i.e.,

a broadcast - entails the allocation of additional data descriptors to act as queue

entries, all set up to point to the same linked-list of packet buffers. The

reference count in the packet buffer will be updated as required for broadcast

frames.

When the frame has been placed on any transmit queue, the firmware also

inspects the status of the corresponding DMA Controller channel . If the channel

is not busy (either receiving a frame, or transmitting a previously queued frame),

then the firmware will load the channel registers with the address of the first

packet buffer in the transmit queue entry at the head of the queue, and enable

the DMA Controller to begin transmitting data on that channel..

17. When the DMA Controller channel is enabled for transmit, the associated MAC

logic attempts to seize the medium and send the data: it defers to passing

frames, if any, waits for the required interframe gap and then starts sending the

802.3 preamble, followed by the frame data. The DMA Controller will read data

out of the packet buffers in memory to fill the MAC channel FIFO with frame

data, traversing the linked-list of buffers until it has reached the end.

If a collision occurs at any time during frame transmit, the MAC channel logic will

terminate the transmission, cause a jam pattern to be sent, and then start the

backoff timer with the pre-loaded backoff value. In the mean time, the DMA

Controller will signal a collision interrupt to the Switch Processor; the Switch

Processor firmware will then re-compute the backoff timer for the next possible

collision and set up the DMA Controller channel registers to re-transmit the

frame after the backoff period ends.

18. The transmit process continues until no more packet buffers remain to be

transmitted. The DMA Controller detects that all the frame data has been

transmitted when it reaches the end of the linked-list of buffers (as indicated by

a NULL NextPB pointer) and the MAC channel FIFO is empty, signifying that the

data have been placed on the medium. At this point, the DMA Controller

interrupts the Switch Processor to notify it that the frame transmit has completed

successfully.

Note that the DMA Controller computes a running CRC over the transmitted

data. If the CRC is found to be in error, the DMA Controller will optionally

append a correct CRC at the end of the frame, if the appropriate mode bit is set

in a configuration register.

19. The Switch Processor responds to the DMA Controller end-of-transmit interrupt

and begins executing the end-of-transmit interrupt service routine firmware. The

firmware first reads the data descriptor at the head of the transmit queue for the

port (which is associated with the frame that was just transmitted), obtains a

pointer to the last packet buffer in the linked-list of buffers holding the

PM3350-SW Datasheet(PDF) 111 Page - PMC-Sierra, Inc

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