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PM3350-SW Datasheet(PDF) 118 Page - PMC-Sierra, Inc |
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PM3350-SW Datasheet(HTML) 118 Page - PMC-Sierra, Inc |
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118 / 224 page ![]() ELAN 8X10 PM3350 ELAN 8 X10 DATA SHEET PMC-970109 ISSUE 3 8 PORT ETHERNET SWITCH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY 116 another device when acting as a destination and acknowledging the receipt of data. This fact is taken advantage of by the ELAN 8x10 hardware: the CTRBASE register in the DMA Controller is set up at configuration time in each ELAN 8x10 device with the offset of the request counter index assigned to the device itself; the firmware then simply has to indicate the target of a request or acknowledge, and the hardware can use the internal CTRBASE register to determine the actual counter to increment. This also facilitates broadcasts, as the firmware can simply supply a bitmask in the CTRMASK DMA Controller register corresponding to the chips that form the target of the broadcast, and the hardware will use the bitmask in conjunction with the CTRBASE register to increment multiple request counters across the system. The foregoing has dealt with the use and configuration of the hardware communication means, i.e., the request and acknowledge counter banks. The situation for the actual data transfer is substantially simpler, as the ELAN 8x10 hardware and firmware place no restrictions on the PCI addresses from which data copies may be done. Once a particular request has been mapped to a specific source chip via the request counter index by any ELAN 8x10 device, the 32-bit PCI address from which the data transfer must be performed is defined by the 32-bit RemoteDD field of the expansion port descriptor assigned to track transfers from that chip. Thus the only hard limitation on the number of devices that may be supported by an ELAN 8x10 system is set by the number of request and acknowledge counters that are implemented in the ELAN 8x10 chips. It should be noted that the assignments of counter indices to devices (as well as the association of devices with actual PCI addresses) is performed statically at initialization time by the boot image executed by every ELAN 8x10 device. General Frame Transfer Sequence The following diagram details the sequence of events when switching a unicast frame from a MAC port on the source ELAN 8x10 device to a MAC port on a remote ELAN 8x10 device via the expansion bus. (The same general sequence holds even if the destination device is not an ELAN 8x10 chip, as all devices that expect to communicate with the ELAN 8x10 must follow the same protocol.) Note that if a broadcast frame is sent to two or more ELAN 8x10 devices, then the frame reception and processing steps remain the same within the source device, but the frame transfer steps are repeated for each additional remote ELAN 8x10 device. |
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