PM3350-SW datasheet(120/224 Pages) PMC

120 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

118

One of the ELAN 8x10 devices in the system (the source device) begins

receiving an Ethernet frame on one of its MAC channels; the frame is intended

for a destination entity connected to a port on another ELAN 8x10 device (the

destination device). The ELAN 8x10 MAC channel converts and places the

incoming data into the MAC interface FIFO, as usual, until the end of the frame

has been reached.

The DMA Controller allocates one or more packet buffers from the free packet

buffer pool to hold the frame and fills them with data words copied from the

MAC channel FIFO, computing the required 32-bit CRC over the frame at the

same time. When the 14-byte frame header has been received, the DMA

Controller uses the hash table lookup mechanism to scan the address table and

obtain the pointers to the source and destination address table entries for the

MAC addresses in the frame. Note that the destination address table entry in

this case must be a forwarding tag, as the frame is destined to be transferred

across the PCI bus to another device. The source address table entry (if one

exists) must be a hash bucket.

The frame reception process continues until the frame has been completely

received and transferred to packet buffers. When reception terminates, the DMA

Controller flushes the MAC FIFO to the packet buffers and notifies the Switch

Processor of the received frame by via an interrupt.

The Switch Processor executes the normal receive interrupt service routine in

response to the interrupt; as usual, it first reads out the contents of the

appropriate DMA Controller channel registers, and then re-enables the DMA

channel. The receive interrupt service firmware checks the status code returned

by the DMA to determine whether the frame is errored, and performs the

necessary processing as indicated.

If a valid frame has been received, the firmware verifies that the port buffer

allocation limit in the MaxBuffers field of the local port descriptor has not been

exceeded (and begins backpressure if necessary, or frame discard if the limit

has been exceeded, as already described).

The receive interrupt service firmware now allocates and initializes a data

descriptor to point to the frame, as usual, and queues it on to tail of the work

queue. The work counter is incremented, generating a work queue interrupt.

When the Switch Processor receives the work interrupt, it begins executing the

work queue interrupt service routine, and will remove the frame from the work

queue and process it. As before, the firmware begins by decoding the source

hash bucket pointer returned by the DMA Controller and checking it for

consistency, and will announce a topology change or learn a new address

based on the results. It will also update the aging timestamp in the source hash

bucket (if a valid one exists). The standard filter check is performed to insure

that the source and destination ports are not the same. The destination address

PM3350-SW Datasheet(PDF) 120 Page - PMC-Sierra, Inc

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