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PM3350-SW Datasheet(PDF) 172 Page - PMC-Sierra, Inc |
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PM3350-SW Datasheet(HTML) 172 Page - PMC-Sierra, Inc |
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172 / 224 page ![]() ELAN 8X10 PM3350 ELAN 8 X10 DATA SHEET PMC-970109 ISSUE 3 8 PORT ETHERNET SWITCH PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY 170 Control Registers The 96 16-bit control registers, cr0 through cr95, provide control and status of the functional blocks comprising the PM3350. The control registers can be read by the RISC only by using MOVE instructions to transfer their contents to the general-purpose registers. The contents of any control register may be accessed or modified by the MOVE and LDI instructions. Some of the control registers may exhibit side effects when written to; these are noted in the register descriptions. Mnemonic Address Register DMCTRL 0x20 DMA control word (cr0) DMSTAT 0x21 DMA status register (cr1) INSTCSR 0x22 RAM/ROM instruction control register (cr2) INSTDATA 0x23 RAM/ROM instruction data register (cr3) DMFLISTL 0x24 DMA freelist pointer low (cr4) DMFLISTH 0x25 DMA freelist pointer high (cr5) MREG_ADDR 0x26 Memory Interface Register Address register (cr6) MREG_DATA 0x27 Memory Interface Register Data register (cr7) 0x28 REQID 0x29 Request info (cr9) ACKID 0x2A Acknowledge info (cr10) TASKCTR 0x2B Task counter (cr11) DMNFREEL 0x2C DMA next free packet buffer low (cr12) DMNFREEH 0x2D DMA next free packet buffer high (cr13) CTRSEL 0x2E Request/ack counter select reg (cr14) CTRDATA 0x2F Request/ack counter data reg (cr15) RPCICMD 0x30 RPCIM command register (cr16) RPCIDATA 0x31 RPCIM Data register (cr17) RPCIADDRL 0x32 RPCIM Address register high (cr18) RPCIADDRH 0x33 RPCIM Address register low (cr19) RPCISTAT 0x34 RPCIM status register (cr20) WTIMER 0x35 RST module: Watchdog Timer (cr21) FRST 0x36 RST module: Firmware RST register (cr22) DBGCTRL 0x37 DBG module Control register (cr23) RAMREGL 0x38 HASH ram register 15:0 (cr24) RAMREGH 0x39 HASH ram register 31:16 (cr25) HCADDR 0x3A HASH control address register (cr26) |
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