PM3350-SW datasheet(169/224 Pages) PMC

169 / 224 page

ELAN 8X10

PM3350 ELAN 8 X10

DATA SHEET

PMC-970109

ISSUE 3

8 PORT ETHERNET SWITCH

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND PMC-SIERRA, INC. CUSTOMERS ONLY

167

This register is reserved for factory test purposes, and should not be modified during

normal operation.

Device Debug Registers

Registers 0x00FF0080 - 0x00FF009C: Debug Control

These registers are used to perform debug of Switch Processor operating code via the

PCI bus interface. They are reserved for factory test purposes, and should not be

modified during normal operation.

Debug control/status register (DIBCTRL):

bit 31

= vector force recognized

bits 30:9

= unused, reserved

bit 8

= vector force enable

bit 7

= instruction cache flush

bit 6

= data cache flush

bit 5

= RISC exception disable

bits 4:3

= unused, reserved

bit 2

= RISC breakpoint halt enable

bit 1

= breakpoint #2 enable

bit 0

= breakpoint #1 enable

Request and Acknowledge Counter Registers

Registers 0x00FFFF00 - 0x00FFFF1C: Request Counters

These counters are used for requests from a source device to a destination device

across the PCI bus. A write (of any arbitrary data) to one of these 32-bit locations

increments the corresponding request counter by one.

Registers 0x00FFFF20 - 0x00FFFF3C: Acknowledge Counters

These counters are used for acknowledges from a destination device to a source

device across the PCI bus. A write (of any arbitrary data) to one of these 32-bit

locations increments the corresponding acknowledge counter by one.

PM3350-SW Datasheet(PDF) 169 Page - PMC-Sierra, Inc

PM3350-SW Datasheet(HTML) 169 Page - PMC-Sierra, Inc

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