PM5313 datasheet(57/646 Pages) PMC

57 / 646 page

PRODUCTION

PMC-Sierra, Inc.

PM5313 SPECTRA-622

DATASHEET

PMC-1981162

ISSUE 6

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

PECL

Input

The receive signal detect PECL input (SD)

indicates the presence of valid receive signal power

from the Optical Physical Medium Dependent

Device. A PECL logic high indicates the presence of

valid data. A PECL logic low indicates a loss of

signal.

In clock recovery mode, when SD is low, the

receive serial data is forced to all zeros and the

phase locked loop switches to the reference clock

(REFCLK+/-) to keep the recovered clock in range.

These inputs must be DC coupled. Please refer to

the Operation section for a discussion of PECL

interfacing issues.

TXD+

TXD-

PECL

Output

The transmit differential data outputs (TXD+/-)

contain the STS-12 (STM-4) 622.08 Mbit/s NRZ

encode bit serial transmit stream. The TXD+/-

outputs are driven using the synthesized clock from

the CSU or the recovery clock from the CRU when

loop timing is enabled. Loop timing is enabled by

setting the LOOPT bit in the SPECTRA-622 Line

Configuration #1 register to logic one. The

TC1J1V1/TFPO output may be used to identify the

frame alignment on TXD+/-. It will rising 15 bits (+/-

3 bits) before the first byte of the SPE.

Please refer to the Operation section for a

discussion of PECL interfacing issues.

SCPO[1]

SCPO[0]

Tristate

Output

The status and control port outputs (SCPO[1:0])

provides two drive points for controlling auxiliary

devices. The signal levels on these outputs

correspond to the bit values contained in the

SPECTRA-622 Serial Control Port Status and

Control register.

SCPO[1:0] can be tristate using the SCPO_TS bit

in the SPECTRA-622 Serial Control Port Status and

Control register. On reset, these outputs will be

tristate by default.

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