PM5313 datasheet(74/646 Pages) PMC

74 / 646 page

PRODUCTION

PMC-Sierra, Inc.

PM5313 SPECTRA-622

DATASHEET

PMC-1981162

ISSUE 6

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

PROPRIETARY AND CONFIDENTIAL

10.5

Receive Transport Overhead Extraction Signals

Pin Name

Type

No.

Function

RSLDCLK

Tristate

Output

C19

The receive section or line data communication

channel (DCC) clock (RSLDCLK) is used to update

the received section or line DCC (RSLD). A smooth

or gapped version of this clock may be selected.

When selecting the smooth clock and clocking the

section DCC, RSLDCLK is a 192 kHz clock with

nominal 50% duty cycle. When selecting to clock

the line DCC, RSLDCLK is a 576 kHz clock with

nominal 50% duty cycle.

When selecting the gapped clock and clocking the

section DCC, RSLDCLK is a 192 kHz clock

generated by gapping a 216 kHz clock. When line

DCC is selected, RSLDCLK is a 576 kHz clock

generated by gapping a 2.16 MHz clock.

In all cases, RSLD is updated on the falling edge of

RSLDCLK. In gapped clock mode, a gap detector

on RSLDCLK is needed to identify the MSB on

RSLD. A edge detection of RFPO may also be

used. In smooth clock mode, RTOHFP may be

sampled high at the same time as the MSB on

RSLD.

The RTOC Overhead Control register contains the

RSLDSEL register bit used to select the section or

line DCC. The same register also contains the

RX_GAPSEL register bit used to select the smooth

or gapped RSLDCLK output clock and the

RSLD_TS register bit that can be used to tri-state

RSLDCLK and RSLD outputs.

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