PM5313 datasheet(81/646 Pages) PMC

81 / 646 page

PRODUCTION

PMC-Sierra, Inc.

PM5313 SPECTRA-622

DATASHEET

PMC-1981162

ISSUE 6

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

PROPRIETARY AND CONFIDENTIAL

10.6

Transmit Transport Overhead Insertion Signals

Pin Name

Type

No.

Function

TSLDCLK

Tristate

Output

B23

The transmit section or line data communication

channel (DCC) clock (TSLDCLK) is used to clock in

the transmit section or line DCC (TSLD). A smooth

or gapped version of this clock may be selected.

When selecting the smooth clock and clocking the

section DCC, TSLDCLK is a 192 kHz clock with

nominal 50% duty cycle. When selecting to clock

the line DCC, TSLDCLK is a 576 kHz clock with

nominal 50% duty cycle.

When selecting the gapped clock and clocking the

section DCC, TSLDCLK is a 192 kHz clock

generated by gapping a 216 kHz clock. When line

DCC is selected, TSLDCLK is a 576 kHz clock

generated by gapping a 2.16 MHz clock.

In all cases, TSLD is sampled on the rising edge of

TSLDCLK. In gapped clock mode, a gap detector

on TSLDCLK is needed to identify when the most

significant bit (MSB) should be present on TSLD.

An edge detection on TFP may also be used. In

smooth clock mode, TTOHFP may be used to

identify the rising edge when the MSB should be

present on TSLD.

The TTOC Overhead Control register contains the

TSLD_SEL register bit used to select the section or

line DCC. The same register also contains the

TX_GAPSEL register bit used to select the smooth

or gapped TSLDCLK output clock and the

TSLD_TS register bit that can be used to tri-state

the TSLDCLK output.

PM5313 Datasheet(PDF) 81 Page - PMC-Sierra, Inc

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