PM5313 datasheet(76/646 Pages) PMC

76 / 646 page

PRODUCTION

PMC-Sierra, Inc.

PM5313 SPECTRA-622

DATASHEET

PMC-1981162

ISSUE 6

SONET/SDH PAYLOAD EXTRACTOR/ALIGNER FOR 622 MBIT/S

PROPRIETARY AND CONFIDENTIAL

Pin Name

Type

No.

Function

RLD

Tristate

Output

D19

The receive line DCC (RLD) bit serial output signal

contains the received line data communication

channel (D4-D12).

RLD is updated on the falling edge of RLDCLK and

should be sampled externally on the rising edge of

RLDCLK.

The RTOC Overhead Control register contains the

RX_GAPSEL register bit used to select the smooth

or gapped RLDCLK output clock and the RLD_TS

and RLD outputs.

ROWCLK

Output

A20

The receive order wire clock (ROWCLK) is used to

update the received section orderwire, user channel

and line orderwire. (RSOW, RSUC and RLOW). A

smooth or gapped version of this clock may be

selected.

When selecting the smooth clock, ROWCLK is a 64

kHz clock with nominal 50% duty cycle.

When selecting the gapped clock, ROWCLK is a 64

kHz clock generated by gapping a 72 kHz clock.

In all cases, RSOW, RSUC and RLOW are updated

on the falling edge of ROWCLK. In gapped clock

mode, a gap detector on ROWCLK is needed to

identify the MSB on RSOW, RSUC and RLOW. A

edge detection of RFPO may also be used. In

smooth clock mode, RTOHFP may be sampled

high at the same time as the MSB on RSOW,

RSUC and RLOW.

The RTOC Overhead Control register contains the

RX_GAPSEL register bit used to select the smooth

or gapped ROWCLK output clock.

PM5313 Datasheet(PDF) 76 Page - PMC-Sierra, Inc

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