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PM7375-SC Datasheet(PDF) 20 Page - PMC-Sierra, Inc

Part # PM7375-SC
Description  LOCAL ATM SAR & PHYSICAL LAYER
PDF  430 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7375-SC Datasheet(HTML) 20 Page - PMC-Sierra, Inc

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PM7375 LASAR-155
DATA SHEET
PMC-931127
ISSUE 6
LOCAL ATM SAR & PHYSICAL LAYER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
4
4
APPLICATION EXAMPLES
The LASAR-155™ is typically used to implement the core of a SONET or SDH
STS-3c/STM-1 or SONET STS-1 ATM User Network Interface by which an ATM
terminal is linked to an ATM switching system. The LASAR-155 can be used in a
network interface card (NIC) or directly on a mother board. Though targeted for a
PCI bus based system, the LASAR-155 can also be used with other host buses
using external glue logic.
On the line side, the LASAR-155 is typically interfaced to UTP-5 twisted pair wiring
via a line receiver, a line driver and transformers. The line receiver should perform
fixed equalization and DC restoration for good bit error rate performance.
Alternatively, the LASAR-155 can be directly connected to an optical datalink. If
required, the LASAR-155 can be loop-timed where the recovered clock is used as
the transmit clock.
On the system side, the LASAR-155 can be directly attached to a PCI bus via the
packet port. An internal DMA controller is provided to support packet segmentation
from packet memory and reassembly to packet memory totally independent of the
PCI Host. PCI Host notification of segmentation and/or reassembly completion can
be on a per packet basis or on a multi packet basis.
The initial configuration and ongoing control and monitoring of the LASAR-155 can
be provided either via the generic microprocessor interface when in slave mode, the
PCI bus packet port when in master mode, or through a combination of both.
In addition, the LASAR-155 can interface to an external PHY device using the
SCI-PHY/Utopia port. The generic microprocessor interface can be configured in
master mode for configuration and ongoing control and monitoring. When this mode
of operation is selected an optional EPROM can also be supported by the generic
microprocessor interface.



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