Electronic Components Datasheet Search
  English  ▼

X  

PM7375-SC Datasheet(PDF) 30 Page - PMC-Sierra, Inc

Part # PM7375-SC
Description  LOCAL ATM SAR & PHYSICAL LAYER
PDF  430 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7375-SC Datasheet(HTML) 30 Page - PMC-Sierra, Inc

Back Button PM7375-SC Datasheet HTML 26Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 27Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 28Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 29Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 30Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 31Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 32Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 33Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 34Page - PMC-Sierra, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 30 / 430 page
background image
PM7375 LASAR-155
DATA SHEET
PMC-931127
ISSUE 6
LOCAL ATM SAR & PHYSICAL LAYER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
TXD+
TXD-
Output
126
127
The transmit differential data outputs (TXD+, TXD-)
contain the 155.52 Mbit/s transmit STS-3c (STM-1)
stream or the 51.84 Mbit/s transmit STS-1 stream.
When the STS-1 stream is selected, TXD+/- are
updated on the falling edge of TXC. TXD+/- is NRZ
encoded.
TCLK
Output
155
The transmit byte clock (TCLK) is either a 19.44 MHz
or a 6.48 MHz clock derived from the transmit line
rate.
TFPO
Output
158
The active high framing position output (TFPO) signal
is an 8 kHz timing marker for the transmitter. TFPO
goes high for a single TCLK period once every 2430 in
STS-3c (STM-1) mode or 810 in STS-1 mode TCLK
cycles. TFPO is updated on the rising edge of TCLK.
RGFC/RLD Output
111
The RGFC/RLD output is a dual function output
controlled using the UNI_POTS bit in the LASAR-155
Master Configuration register.
When the UNI_POTS bit is low, the receive generic
flow control (RGFC) output presents the extracted GFC
bits in a serial stream. The four GFC bits are
presented for each received cell, with the RCP output
indicating the position of the most significant bit. The
updating of RGFC by particular GFC bits may be
disabled through the RACP Configuration register. The
serial link is forced low if cell delineation is lost. RGFC
is updated on the rising edge of RCLK.
When the UNI_POTS bit is high, the receive line DCC
(RLD) signal contains the serial line data
communications channel (D4 - D12) extracted from the
incoming stream. RLD is updated on the falling edge
of RLDCLK.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com