PM7375-SC datasheet(26/430 Pages) PMC

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PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

high or low priority ready queue. The LASAR-155 automatically appends the AAL-5

trailer, segments the packet and subjects the cells to either peak cell rate or

sustainable cell rate enforcement.

The LASAR-155 generates most of a cell's header using the transmit parameter

table. The generic flow control (GFC) bits may optionally be inserted using a

dedicated serial port. The header error code (HEC) is automatically calculated and

inserted. The cell payload is optionally scrambled. Generated transmit cells are

automatically inserted into a STS-3c (STM-1) or STS-1 SONET/SDH Synchronous

Payload Envelope (SPE). In the absence of transmit cells, the LASAR-155

automatically inserts Idle/unassigned cells into the SPE.

The LASAR-155 transmits SONET/SDH frames, via a bit serial interface, and

formats SONET section, line, and path overhead appropriately. It performs framing

pattern insertion (A1, A2), scrambling, alarm signal insertion, and creates section,

line, and path bit interleaved parity (B1, B2, B3) as required to allow performance

monitoring at the far end. Line and path far end block error indications (Z2, G1) are

also inserted. The LASAR-155 generates the payload pointer (H1, H2) and inserts

the synchronous payload envelope which carries the ATM cell payload.

For system diagnostics, the LASAR-155 supports the insertion of a variety of errors

into the transmit stream, such as framing pattern errors, bit interleaved parity errors

and illegal pointers.

No auxiliary line clocks are required directly by the LASAR-155 as it is capable of

synthesizing the line rate transmit clock and recovering the receive clock using

either a 19.44 MHz or 6.48 MHz reference clock. The LASAR-155 is configured,

controlled and monitored via either the generic microprocessor port interface in

slave mode or the PCI bus interface in master mode. In slave mode, a mailbox

scheme with shared buffers is provided for communication between the

microprocessor and PCI Host.

The LASAR-155 can interface with external devices when the generic

microprocessor port interface is configured for master mode operation. In this mode

the PCI Host configures, controls and monitors the LASAR-155 and the external

devices.

The LASAR-155 is implemented in low power, 0.6 micron, +5 Volt CMOS

technology. It has TTL and pseudo ECL (PECL) compatible inputs and outputs and

is packaged in a 208 pin copper slugged plastic QFP package.

PM7375-SC Datasheet(PDF) 26 Page - PMC-Sierra, Inc