PM7375-SC datasheet(31/430 Pages) PMC

31 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

RCP/

RLDCLK

Output

110

The RCP/RLDCLK output is a dual function output

controlled using the UNI_POTS bit in the LASAR-155

Master Configuration register.

When the UNI_POTS bit is low, the receive cell pulse

(RCP) indicates the location of the four GFC bits in the

RGFC serial stream. RCP is coincident with the most

significant GFC bit. RCP is updated on the rising edge

of RCLK.

When the UNI_POTS bit is high, the receive line DCC

clock (RLDCLK) is a 576 kHz clock used to update the

RLD output. RLDCLK is generated by gapping a

2.16 MHz clock.

TGFC/TLD

Input

113

The TGFC/TLD input is a dual function input controlled

using the UNI_POTS bit in the LASAR-155 Master

Configuration register.

When the UNI_POTS bit is low, the transmit generic

flow control (TGFC) input provides the ability to insert

the GFC value. The four TCLK periods following the

TCP output pulse contain the GFC value to be

inserted into the current cell. The GFC enable bits of

the TACP Configuration register enable the insertion of

each serial bit. TGFC is sampled on the rising edge of

TCLK.

When the UNI_POTS bit is high, the transmit line

DCC (TLD) signal contains the serial line data

communications channel (D4 - D12). TLD is sampled

on the rising edge of TLDCLK.

PM7375-SC Datasheet(PDF) 31 Page - PMC-Sierra, Inc