Electronic Components Datasheet Search
  English  ▼

X  

PM7375-SC Datasheet(PDF) 45 Page - PMC-Sierra, Inc

Part # PM7375-SC
Description  LOCAL ATM SAR & PHYSICAL LAYER
PDF  430 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM7375-SC Datasheet(HTML) 45 Page - PMC-Sierra, Inc

Back Button PM7375-SC Datasheet HTML 41Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 42Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 43Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 44Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 45Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 46Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 47Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 48Page - PMC-Sierra, Inc PM7375-SC Datasheet HTML 49Page - PMC-Sierra, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 45 / 430 page
background image
PM7375 LASAR-155
DATA SHEET
PMC-931127
ISSUE 6
LOCAL ATM SAR & PHYSICAL LAYER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
29
REQB
Output 201
The active low PCI bus request (REQB) signal is used
by the LASAR-155 to request an external arbiter for
control of the PCI bus. REQB is forced low when the
internal PCI DMA controller requires access to the
packet memory. Otherwise, REQB is forced high.
REQB is updated on the rising edge of PCICLK.
GNTB
Input
200
The active low PCI bus grant (GNTB) signal is used to
grant control of the PCI to the LASAR-155 in response
to a bus request via the REQB output. When GNTB is
high, the LASAR-155 does not control the PCI bus
and thus must wait. When GNTB is low, the external
arbiter has granted the LASAR-155 control of the PCI
bus. However, the LASAR-155 does not proceed until
the FRAMEB signal is high indicating no current
transactions.
GNTB is sampled using the rising edge of PCICLK.
PERRB
Output
35
The active low parity error (PERRB) signal indicates
when the LASAR-155 detects a parity error over the
AD[31:0] and C/BEB[3:0] signals when compared to
the PAR input. PERRB is high when no parity error is
detected. PERRB is forced low for the cycle
immediately following the offending PAR cycle.
PERRB is enabled using a bit in the Control register in
the PCI Configuration registers space. In addition,
regardless of whether output, PERRB is enabled or
not, parity errors are indicated in the Status register in
the PCI Configuration registers space.
PERRB is updated on the rising edge of PCICLK.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com