PM7375-SC datasheet(80/430 Pages) PMC

80 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

9.14.4 Transmit Queues and Operation

TDRs describing TD of packet(s) are passed from the PCI Host to the TRM using

the Transmit Descriptor Reference Ready (TDRR) Queues found in the PCI Host

memory. Two ready queues are provided, a high priority and a low priority queue.

TDs in the high priority queue get queued for transmission before TDs in the low

priority queue. When packets associated with descriptors are transmitted is

determined by the Transmit ATM Traffic Shaper (TATS) block.

TDRs describing TD of packet(s) that have been segmented and transmitted are

passed from the TRM to the PCI Host using the Transmit Descriptor Reference Free

(TDRF) Queue found in the PCI Host memory. Some buffering of TDs being

returned to the TDRF Queue is optionally provided to decrease PCI bus accesses.

All three queues are defined using a common base pointer residing in the PCID

Transmit Queue Base register and twelve offset pointers, four per queue. For each

queue, two pointers are required to define the start and the end of a queue while

two pointers are required for the current write and read locations within the queue.

The read pointer always points to the last location read while the write pointer

always points to the next location to be written.

A full condition for the queues is defined as the read and the write pointers being

equal. An empty condition is defined as the read pointer one less then the write

pointer. The last location in a queue is not considered as part of the queue and thus

is not a valid entry.

Packets are assembled in PCI Host memory using TDs. Each TD contains control

fields, a TD pointer reference field and a buffer pointer field. The control fields can

be used by the PCI Host to associate a packet with an open VC and to inform the

LASAR-155 how to segment the packet. If a packet requires more memory then

available in the buffer referenced by the current TD, the PCI Host can link a new TD

to the current TD using the current TD's TD pointer reference. When the PCI Host

needs to transmit a packet, it formats a TD and adds the TD's TDR to the high or

low priority TDRR Queue as shown below.

Once the TRM is notified that a packet has been added onto the TDRR Queue, it

removes the TDR from the TDRR Queues, verifies that the VC the current packet is

associated with is in fact open and adds the TDR to its internal transmit VC queues.

Segmentation of the packet then proceeds at the negotiated VC traffic parameters

as controlled by the TATS block. As TD buffers are consumed and become empty,

the TRM attaches the TD's TDR to the TDRF Queue and indicates the success of

the packet transmission in the TDR. In order to take advantage of burst PCI

transfers, the TRM optionally buffers up to six TDs before attaching them to the

TDRF Queue. If TD buffering is enabled, the TDs are flushed to the TDRF Queue

PM7375-SC Datasheet(PDF) 80 Page - PMC-Sierra, Inc

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