PM7375-SC datasheet(58/430 Pages) PMC

58 / 430 page

PM7375 LASAR-155

DATA SHEET

PMC-931127

ISSUE 6

LOCAL ATM SAR & PHYSICAL LAYER

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

FUNCTIONAL DESCRIPTION

9.1

Receive Line Interface

The Receive Line Interface block performs clock and data recovery and performs

serial to parallel conversion. The clock and data recovery unit can be bypassed

using primary inputs to allow interworking the LASAR-155 with an external CRU.

9.1.1 Clock Recovery Unit

The clock recovery unit recovers the clock from the incoming bit serial data stream.

The clock recovery unit is fully compliant with SONET and SDH jitter tolerance

requirements. The clock recovery unit utilizes a low frequency reference clock to

train and monitor its clock recovery PLL. Under loss of signal conditions, the clock

recovery unit will continue to output a line rate clock that is locked to this reference

for keep alive purposes. The clock recovery unit can be configured to utilize

reference clocks at 6.48 or 19.44 MHz. The clock recovery unit also supports

diagnostic loopback and a loss of signal input that squelches normal input data.

Initially, the PLL locks to the reference clock, RRCLK+/-. When the frequency of the

recovered clock is within 488 ppm of the reference clock, the PLL attempts to lock

to the data. Once in data lock, the PLL reverts to the reference clock if no data

transitions occur in 80 bit periods or if the recovered clock drifts beyond 488 ppm of

the reference clock.

When the transmit clock is derived from the recovered clock (loop timing), the

accuracy of the transmit clock is directly related to the RRCLK+/- reference accuracy

in the case of a loss of signal condition. In applications that are required to meet the

Bellcore GR-253-CORE SONET Network Element free-run accuracy specification,

the reference must be within +/-20 ppm. When not loop timed, the RRCLK+/-

accuracy may be relaxed to +/-50 ppm.

The loop filter transfer function is optimized to enable the PLL to track the jitter, yet

tolerate the minimum transition density expected in a received SONET data signal.

The total loop dynamics of the clock recovery PLL yield a jitter tolerance which

exceeds the minimum tolerance proposed for SONET equipment by GR-253-CORE

(Figure 9.1). The jitter tolerance illustrated is associated with the external loop filter

components recommended in the Operation section.

PM7375-SC Datasheet(PDF) 58 Page - PMC-Sierra, Inc