SI3233 datasheet(85/100 Pages) SILABS

85 / 100 page

Si3233

Preliminary Rev. 0.5

4. Indirect Registers

Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A

write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the

contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update.

A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the

value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of

16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an

interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.

All values are represented in twos-complement format.

Note:

The values of all indirect registers are undefined following the reset state.

4.1. Oscillators

See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing

Note:

The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read

and written but should be written to zeroes.

Table 30. Si3230 to Si3233 Indirect Register Cross Reference

Si3230

Indirect

Si3233

Indirect

Name

Si3230

Indirect

Si3233

Indirect

Name

Si3230

Indirect

Si3233

Indirect

Name

OSC1

ADCG

NQ34

OSC1X

LCRT

NQ56

OSC1Y

RPTP

VCMR

OSC2

CML

VMIND

OSC2X

CMH

LCRTL

OSC2Y

PPT12

FSK0X

ROFF

PPT34

100

FSK0

RCO

PPT56

101

FSK1X

RNGX

NCLR

102

FSK1

RNGY

NRTP

103

FSK01

DACG

NQ12

104

FSK10

Table 31. Oscillator Indirect Registers Summary

Addr D15

D14

D13

D12

D11

D10

OSC1[15:0]

OSC1X[15:0]

OSC1Y[15:0]

OSC2[15:0]

OSC2X[15:0]

OSC2Y[15:0]

ROFF[5:0]

SI3233 Datasheet(PDF) 85 Page - Silicon Laboratories

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