SI3233 datasheet(89/100 Pages) SILABS

89 / 100 page

Si3233

Preliminary Rev. 0.5

4.4. FK Control

For detailed instructions on FSK signal generation, refer to “Application Note 32: FSK Generation” (AN32). These

registers support enhanced FSK generation mode, which is enabled by setting FSKEN = 1 (direct Register 108,

bit 6) and REL = 1 (direct Register 32, bit 6).

Power Alarm Threshold for Transistors Q3 and Q4.

Power Alarm Threshold for Transistors Q5 and Q6.

Loop Closure Filter Coefficient.

Ring Trip Filter Coefficient.

Thermal Low Pass Filter Pole for Transistors Q1 and Q2.

Thermal Low Pass Filter Pole for Transistors Q3 and Q4.

Thermal Low Pass Filter Pole for Transistors Q5 and Q6.

Common Mode Bias Adjust During Ringing.

Recommended value of 0 decimal.

DC-DC Converter VOV Voltage (Si3233 only).

This register sets the overhead voltage, VOV, to be supplied by the dc-dc converter. When the VOV

bit = 0 (direct Register 66, bit 4), VOV should be set between 0 and 9 V (VMIND = 0 to 6h). When the

VOV bit = 1, VOV should be set between 0 and 13.5 V (VMIND = 0 to 9h).

Loop Closure Threshold—Lower Bound.

This register defines the lower threshold for loop closure hysteresis, which is enabled in bit 0 of

direct Register 108. The range is 0–80 mA in 1.27 mA steps.

Table 37. FSK Control Indirect Registers Summary

Addr D15

D14

D13

D12

D11

D10

FSK0X[15:0]

FSK0[15:0]

FSK1X[15:0]

FSK1[15:0]

FSK01[15:0]

FSK10[15:0]

Table 36. SLIC Control Indirect Registers Description (Continued)

Addr

Description

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