| Electronic Components Datasheet Search |
|
SI3233 Datasheet(PDF) 44 Page - Silicon Laboratories |
|
|
|||||||||||||||||||||||||||||
SI3233 Datasheet(HTML) 44 Page - Silicon Laboratories |
|
44 / 100 page ![]() Si3233 44 Preliminary Rev. 0.5 Reset settings = 0000_1000 Register 10. Two-Wire Impedance Synthesis Control Bit D7D6D5D4D3D2 D1 D0 Name CLC[1:0] TISE TISS[2:0] Type R/W R/W R/W Bit Name Function 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation. 00 = Off 01 = 4.7 nF 10 = 10 nF 11 = Reserved 3TISE Two-Wire Impedance Synthesis Enable. 0 = Two-wire impedance synthesis disabled. 1 = Two-wire impedance synthesis enabled. 2:0 TISS[2:0] Two-Wire Impedance Synthesis Selection. 000 = 600 Ω 001 = 900 Ω 010 = Japan (600 Ω + 1 µF); requires RZREF =12kΩ and C3, C4 = 100 nF 011 = 900 Ω + 2.16 µF; requires RZREF =18kΩ and C3, C4 = 220 nF 100 = CTR21 270 Ω + (750 Ω || 150 nF) 101 = Australia/New Zealand 220 Ω + (820 Ω || 120 nF) 110 = Slovakia/Slovenia/South Africa 220 Ω + (820 Ω || 115 nF) 111 = China 200 Ω + (680 Ω || 100 nF) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |