SI3233 datasheet(25/100 Pages) SILABS

25 / 100 page

Si3233

Preliminary Rev. 0.5

is desired since the regulator output voltage has long settling time constants (on the order of tens of milliseconds)

and cannot change rapidly for TRACK = 1 mode. Therefore, the brief on-hook voltage measurement would yield

approximately the same voltage as the off-hook line voltage and would cause the terminal equipment to incorrectly

sense another off-hook terminal.

Figure 10. VTIP, VRING, and VBAT in the Forward Active State

Table 24. Associated Relevant DC-DC Converter Registers

Parameter

Range

Resolution

Location

DC-DC Converter Power-off

Control

n/a

DCOF

Direct Register 14

DC-DC Converter Calibration

Enable/Status

n/a

DCCAL

Direct Register 93

DC-DC Converter PWM Period

0 to 15.564 us

61.035 ns

DCN[7:0]

Direct Register 92

DC-DC Converter Min. Off Time

(0 to 1.892 us) +

4 clock cycles

61.035 ns

DCTOF[4:0]

Direct Register 93

High Battery Voltage—VBATH

0 to –94.5 V

1.5 V

VBATH[5:0]

Direct Register 74

Low Battery Voltage—VBATL

0 to –94.5 V

1.5 V

VBATL[5:0]

Direct Register 75

VOV

0 to –9 V or

0 to –13.5 V

1.5 V

VMIND[3:0]

VOV

Indirect Register 64

Direct Register 66

Note:

The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped

directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through

31).

Constant I Region

Constant V Region

LIM

RING

BAT

BATL

LOOP

TIP

TRA

CK=

TRACK=0

TIP - VRING|

SI3233 Datasheet(PDF) 25 Page - Silicon Laboratories

SI3233 Datasheet(HTML) 25 Page - Silicon Laboratories

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

Datasheet Download

Link URL