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SI3233 Datasheet(PDF) 41 Page - Silicon Laboratories |
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SI3233 Datasheet(HTML) 41 Page - Silicon Laboratories |
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41 / 100 page ![]() Si3233 Preliminary Rev. 0.5 41 101 Common Mode Loop Current Gain Calibration Result CALGC[4:0] 102 Current Limit Calibration Result CALGIL[3:0] 103 Monitor ADC Offset Calibration Result CALMG1[3:0] CALMG2[3:0] 104 Analog DAC/ADC Offset DACP DACN ADCP ADCN 105 DAC Offset Calibration Result DACOF[7:0] 106 Common Mode Balance Calibration Result CMBAL[5:0] 107 DC Peak Voltage Calibration Result CMDCPK[3:0] 108 Enhancement Enable ILIMEN FSKEN DCSU LCVE DCFIL HYSTEN Table 29. Direct Register Summary (Continued) Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 |
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