SI3233 datasheet(29/100 Pages) SILABS

29 / 100 page

Si3233

Preliminary Rev. 0.5

2.4.4. Enhanced FSK Waveform Generation

Enhanced FSK generation can be enabled by setting

FSKEN = 1 (direct Register 108, bit 6) and REL = 1

(direct Register 32, bit 6). In this mode, the user can

define mark (1) and space (0) attributes once during

initialization by defining indirect registers 69–74. The

user need only indicate 0-to-1 and 1-to-0 transitions in

the information stream. By writing to FSKDAT (direct

tone generator 1 to give additional resolution to timers

and frequency generation. “AN32: Si321x Frequency

Shift

Keying

(FSK)

Modulation”

gives

detailed

instructions on how to implement FSK in this mode.

Additionally, sample source code is available from

Silicon Laboratories upon request.

2.4.5. Tone Generator Interrupts

Both the active and inactive timers can generate their

own interrupt to signal “on/off” transitions to the

software. The timer interrupts for tone generator 1 can

be individually enabled by setting the O1AE and O1IE

bits (direct Register 21, bits 0 and 1, respectively).

Timer interrupts for tone generator two are O2AE and

O2IE (direct Register 21, bits 2 and 3, respectively). A

pending interrupt for each of the timers is determined by

reading the O1AP, O1IP, O2AP, and O2IP bits in the

Interrupt Status 1 register (direct Register 18, bits 0

through 3, respectively).

2.5. Ringing Generation

The ProSLIC provides fully programmable internal

balanced ringing with or without a dc offset to ring a

wide variety of terminal devices. All parameters

associated with ringing are software programmable:

ringing frequency, waveform, amplitude, dc offset, and

ringing cadence. Both sinusoidal and trapezoidal ringing

waveforms are supported, and the trapezoidal crest

factor is programmable. Ringing signals of up to 88 V

peak or more can be generated, enabling the ProSLIC

to drive a 5 REN (1380

Ω + 40 µF) ringer load across

loop lengths of 2000 feet (160

Ω) or more.

2.5.1. Ringing Architecture

The ringing generator architecture is nearly identical to

that of the tone generator. The sinusoid ringing

waveform is generated using an internal two-pole

resonance

oscillator

circuit

with

programmable

frequency and amplitude. However, since ringing

frequencies are very low compared to the audio band

signaling

frequencies,

the

ringing

waveform

generated at a 1 kHz rate instead of 16 kHz.

The ringing generator has two timers that function the

same as for the tone generator timers. They allow on/off

cadence settings up to 8 seconds on/ 8 seconds off. In

addition to controlling ringing cadence, these timers

control the transition into and out of the ringing state.

Table 26 summarizes the list of registers used for

ringing generation.

Note:

Tone generator 2 should not be enabled concurrently

with the ringing generator due to resource sharing

within the hardware.

Table 26. Registers for Ringing Generation

Parameter

Range/ Description

Bits

Location

Ringing Waveform

Sine/Trapezoid

TSWS

Direct Register 34

Ringing Voltage Offset Enable

Enabled/

Disabled

RVO

Direct Register 34

Ringing Active Timer Enable

Enabled/

Disabled

RTAE

Direct Register 34

Ringing Inactive Timer Enable

Enabled/

Disabled

RTIE

Direct Register 34

Ringing Oscillator Enable

Enabled/

Disabled

ROE

Direct Register 34

Ringing Oscillator Active Timer

0 to 8 seconds

RAT[15:0]

Direct Registers 48 and 49

Ringing Oscillator Inactive Timer

0 to 8 seconds

RIT[15:0]

Direct Registers 50 and 51

Linefeed Control (Initiates Ringing State)

Ringing State = 100b

LF[2:0]

Direct Register 64

High Battery Voltage

0 to –94.5 V

VBATH[5:0]

Direct Register 74

Ringing dc voltage offset

0 to 94.5 V

ROFF[15:0]

Indirect Register 6

Ringing frequency

15 to 100 Hz

RCO[15:0]

Indirect Register 7

SI3233 Datasheet(PDF) 29 Page - Silicon Laboratories

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