TMPR3911 datasheet(117/462 Pages) TOSHIBA

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Chapter 4 BIU Module

4-17

4.3.3

CS3-CS0 and MCS3-MCS0 Timing

Figure 4.3.1 through Figure 4.3.4 show the timing for CS3-CS0 and MCS3-MCS0. The timing is the

same for all these signals, with the only exception being that 32-bit port timing only applies to CS3-CS0

while 16-bit port timing applies to CS3-CS0 and MCS3-MCS0.

Timing is also shown for Read Page Mode accesses. If Read Page Mode is enabled, the chip select

will be asserted for the entire read cycle. If the processor is performing a burst read to re-fill either a

data or instruction cache line, the chip select will remain asserted for the entire burst read. The first

access of a Read Page Mode access uses the ACCVAL1 control bits to define the access time, while the

next three accesses will use the ACCVAL2 control bits to define the access time. The pattern will repeat

until the read is complete.

Figure 4.3.1 shows the timing for a single Word read and write for a 32-bit memory device. The

access time is defined using the ACCVAL1 control bits. There are separate ACCVAL1 control bits for

each of the chip selects, such that each chip select has an independently configurable access time. The

ACCVAL1 bits should be set to the desired number of CLK times for the chip select. The ACCVAL1

bits must not be set to $0.

Figure 4.3.2 shows the timing for a Word read from a 16-bit port. The access is split into two parts to

read the full 32 bits. During the first read HA (1) will be low and during the second read HA (1) will be

high. The input data path will latch both accesses and concatenate them together as 32 bits for the

processor before asserting the Ack signal to the CPU Interface logic.

Figure 4.3.3 shows a 4-Word burst read from a 32-bit port. The ALE signal is only asserted at the

beginning of the cycle since the upper address bits will not be changed during the burst. The burst will

always start on a 16-byte boundary. The address bits will increment as follows: HA[3:2]

= 00, HA[3:2]

= 01, HA[3:2] = 10, then HA[3:2] = 11.

Figure 4.3.4 shows the same 4-Word burst read from a 32-bit port, except this time Read Page Mode

is enabled. In this case the chip select will remain asserted for the entire access and the addresses will

change to access the new address location. The first access uses the ACCVAL1 control bits, while the

next three accesses use the ACCVAL2 control bits. If the burst had been longer then 4 Words, the

ACCVAL1 control bits would have been used for every fourth access. This type of bursting is

compatible with ROM devices that support page mode access. If the 4-Word burst would have been

from a 16-bit port, eight accesses would have been required, but the ACCVAL1 bits would still be used

for the first and fifth access, while the ACCVAL2 bits would have been used for the rest. If Read Page

Mode is enabled for a particular chip select, then the ACCVAL1 and ACCVAL2 control bits must not

be set to $0. The “up arrow” markings on DCLKOUT in Figure 4.3.1 through Figure 4.3.4 show the

points where input data is sampled.

TMPR3911 Datasheet(PDF) 117 Page - Toshiba Semiconductor