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TMPR3911 Datasheet(PDF) 165 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 165 Page - Toshiba Semiconductor |
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165 / 462 page ![]() Chapter 6 Clock Module 6-3 6.2 Implementation 6.2.1 Block Diagram IRCLK SIBMCLKDIV[2:0] CHI Master Clock SYSCLK SLOWBUS(*2) RF[1:0](*1) OSC PLL (×8) High Rate Clock Enable Logic SIBMCLKDIR SIBMCLK SIB Interface CORECLK CLK2X CLK ENABLE CLK MEMPOWERDOWN RESET FREECLK XHFREE Prgm.Divider ENVIDCLK MUX MUX DIVMOD(*4) VIDEO Module VIDCLK Prgm.Divider ENSIBMCLK SIB Master Clock VIDRF[1:0](*3) SIBSCLK SIBSYNC CHICLKDIR CHICLK Prgm.Divider ENCHIMCLK CHICLKDIV[7:0] CHI module CHIFS MUX Prgm.Divider ENCSERCLK CSERCLKDIV[2:0] MUX CSERCLK CHIMCLKSEL CSERSEL 1/2 or 1/4 (*6) IR module UARTA module UARTB module MAGIC BUS module UARTACLK UARTBCLK ENIRCLK ENUARTACLK ENUARTBCLK 1/32 ENTIMERCLK 1/5 TIMER module SPI module ENSPICLK Magicbus Master Clock Timer Master Clock SPI Master Clock ENMBUSCLK DCLKDISABLE (*5) STOPCPU DCLKOUT 1/2 1/2 VCC3 Figure 6.2.1 Clock Module Block Diagram |
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