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TMPR3911 Datasheet(PDF) 166 Page - Toshiba Semiconductor |
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TMPR3911 Datasheet(HTML) 166 Page - Toshiba Semiconductor |
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166 / 462 page ![]() Chapter 6 Clock Module 6-4 RF[1:0]* 1 SLOWBUS* 2 CORECLK DCLKOUT CLK2X FREECLK CLK XHFREE 00 0 F F F F F/2 F/2 01 0 F/2 F/2 F/2 F F/4 F/2 10 0 F/4 F/4 F/4 F F/8 F/2 11 0 F/8 F/8 F/8 F F/16 F/2 00 1 F/2 F/2 F/2 F F/4 F/2 01 1 F/4 F/4 F/4 F F/8 F/2 10 1 F/8 F/8 F/8 F F/16 F/2 11 1 F/16 F/16 F/16 F F/32 F/2 VIDRF[1:0]* 3 VIDCLK 00 F/2 01 F/4 10 F/8 11 F/16 Note: *1 RF[1:0] is defined by the Config Register in TX39/H Core. *2 SLOWBUS is defined by the Power Control Register in Power Module. *3 VIDRF[1:0] is defined by the Power Control Register in Power Module. *4 DIVMOD is defined by the Power Control Register in Power Module. *5 DCLKDISABLE is defined by the Memory Configuration 3 Register. *6 1/2: TMPR3912XB-92/AU-92 1/4: TMP3911BU/BXB |
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