TMPR3911 datasheet(170/462 Pages) TOSHIBA

170 / 462 page

Chapter 6 Clock Module

6-8

SIBMCLKDIV[2:0]:

These bits define the divide-modulus for the programmable divider used to generate SIBMCLK.

The divide-modulus is equal to (SIBMCLK+2). (See the following table.)

SIBMCLKDIV

divide-modulus

CSERSEL:

Clearing this bit to a logic “0” selects the external SIBMCLK source to be the CSERCLK master

clock. Setting this bit to a logic “1” selects an internal clock source to be the CSERCLK master

clock.

CSERDIV[2:0]:

These bits define the divide-modulus for the programmable divider used to generate CSERCLK.

The divide-modulus is equal to (CSERDIV+2). (See the following table.)

CSERDIV

divide-modulus

ENCSERCLK:

This bit is used to enable or disable the CSERCLK counter. Setting this bit to a logic “1” enables

the CSERCLK counter. Clearing this bit to a logic “0” disables the CSERCLK counter.

ENIRCLK:

This bit is used to enable or disable the IRCLK clock generation. Setting this bit to a logic “1”

enables the IRCLK generation. Clearing this bit to a logic “0” disables the IRCLK generation,

halting the clock to the IR Module in order to reduce power consumption.

ENUARTACLK:

This bit is used to enable or disable the UARTACLK clock generation. Setting this bit to a logic

“1” enables the UARTACLK generation. Clearing this bit to a logic “0” disables the UARTACLK

generation, halting the clock to the UARTA Module in order to reduce power consumption.

ENUARTBCLK:

This bit is used to enable or disable the UARTBCLK clock generation. Setting this bit to a logic

“1” enables the UARTBCLK generation. Clearing this bit to a logic “0” disables the UARTBCLK

generation, halting the clock to the UARTB Module in order to reduce power consumption.

TMPR3911 Datasheet(PDF) 170 Page - Toshiba Semiconductor