TMPR3911 datasheet(171/462 Pages) TOSHIBA

171 / 462 page

Chapter 6 Clock Module

6-9

Table 6.3.1 through Table 6.3.3 show examples of the frequencies for each clock.

Table 6.3.1 Clock Frequencies (1)

DIVMOD = 0, CHIMCLKSEL = 0, CSERSEL = 1, RF[1:0] = 00, SLOWBUS = 0

Frequency

Clock

Symbol

Calculation

setting value

Frequency (MHz)

SYSCLK (External Crystal)

fIN

–

7.3728

9.216

11.520

DCLKOUT (SDRAM Clock)

fDCLKOUT

fIN × 8

58.9824

73.728

92.160

CLK

fCLK

fIN × 4

29.4912

36.864

46.080

CLK2X

fCLK2X

fIN × 8

58.9824

73.728

92.160

XHFREE

fXHFREE

fIN × 4

29.4912

36.864

46.080

FREECLK

fFREECLK

fIN × 8

58.9824

73.728

92.160

VIDCLK (VIDEO Master

Clock)

fVIDCLK

fXHFREE ÷ (2^VIDRF[1:0])

VIDRF

= 00

29.4912

14.7456

7.3728

3.6864

36.864

18.432

9.216

4.608

46.080

23.040

11.520

5.760

SIBMCLK (SIB Master Clock)

fSIBMCLK

fCLK2X ÷ (SIBMCLKDIV[2:0] + 2)

SIBMCLKDIV

000

001

010

011

100

101

110

111

29.4912

19.6608

14.7456

11.7965

9.8304

8.4261

7.3728

–

36.864

24.576

18.432

14.746

12.288

10.532

9.216

–

46.080

30.720

23.040

18.432

15.360

13.166

11.520

–

CHICLK (CHI Clock)

fCHICLK

fCLK ÷ (CHICLKDIV[7:0] + 2)

CHICLKDIV

$00

∼

$FE

14.7456

∼

0.1152

18.432

∼

0.144

23.040

∼

0.180

fCLK2X ÷ 4 (3911BU/BXB)

14.7456

18.432

–

CSERCLK

fCSERCLK

fCLK2X ÷ 2 (AU-92/XB-92)

–

46.08

IRCLK (IR Master Clock)

fIRCLK

fCSERCLK ÷ (CSERDIV[2:0] + 2)

UARTACLK

(UART-A Master Clock)

fUARTACLK

fCSERCLK ÷ (CSERDIV[2:0] + 2)

UARTBCLK

(UART-B Master Clock)

fUARTBCLK

fCSERCLK ÷ (CSERDIV[2:0] + 2)

CSERDIV

= 000

001

010

011

100

101

110

111

7.3728

4.9152

3.6864

2.94912

2.4576

2.1065

1.8432

–

9.216

6.144

4.608

3.6864

3.072

2.633

2.304

–

23.04

15.36

11.52

9.216

7.680

6.5829

5.760

–

MBUSMCLK

(Magic Bus Master Clock)

fMBUSMCLK

fCLK

29.4912

36.864

46.089

TIMERCLK

(Timer Master Clock)

fTIMERCLK

fCLK ÷ 32

0.9216

1.152

1.440

SPIMCLK

(SPI Master Clock)

fSPIMCLK

fCLK ÷ 5

5.8982

7.3728

9.216

SYSCLK (External Crystal)

fIN

–

7.3728

9.216

11.520

DCLKOUT (SDRAM Clock)

fDCLKOUT

fIN × 4

29.4912

36.864

46.080

CLK

fCLK

fIN × 2

14.7456

18.432

23.040

CLK2X

fCLK2X

fIN × 4

29.4912

36.864

46.080

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