TMPR3911 datasheet(175/462 Pages) TOSHIBA

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Chapter 7 CHI Module

7-1

CHI Module

7.1

Overview

The CHI Module within the TMPR3911/12 contains holding registers, shift registers, DMA support, and

other logic to support interfacing to external full-duplex serial TDM communication peripherals, including

ISDN communication devices and PCM/TDM serial highways. The TMPR3911/12 implementation of the

CHI Module is based on the Concentration Highway Interface standard specified by Intel and AT&T, which

is intended to allow glueless interface to various TDM highways used by numerous commercial products.

The TMPR3911/12 CHI Module can also be used to support an intra-system high-speed serial DMA channel

within a PIC system.

The TMPR3911/12 CHI Module utilizes a 4-signal interface consisting of clock, sync, transmit serial data,

and receive serial data. The data is organized as a TDM format, with up to 64 timeslots (nominally 8 bits

each) per frame, with a nominal frame rate of 8 kHz (8 bits

× 8 kHz = 64 kbps nominal data rate per

channel). Up to four input timeslots and up to four output timeslots can be independently selected in each

half-frame. The CHI Module does not handle the timeslots which are not selected for input or output. The

number of timeslots and the data rate (up to 4.096 Mbps) and frame rate (up to 64 kHz, depending on the

system configuration) are programmable, providing flexibility for supporting various TDM communication

peripherals. These timeslots are commonly used to carry voice, data, or control and status information.

The CHI Module provides full-duplex DMA support for receive and transmit (two DMA channels). The

DMA buffers can be configured in a continuous (circular) buffer mode or a one-time (empty or fill, then

stop) buffer mode. Half-buffer and end-of-buffer DMA address counter interrupts are available, allowing the

CPU to minimize overhead and efficiently empty or fill half of the DMA buffer in a ping-pong fashion. The

DMA buffer size is programmable (up to a maximum of 16 Kbytes) and the receive and transmit buffers can

be configured to either reside in different memory spaces or share the same memory space (overlapping

buffers for loopback purposes or for optimum memory allocation). Also available is a direct CPU read/write

mode for bypassing the DMA, allowing the CPU to read or write the CHI data on a sample by sample basis,

if so desired.

7.1.1

Related Pins

CHIFS:

INPUT/OUTPUT

This pin is the CHI frame synchronization signal. This pin is available for use in one of two

modes. As an output, this pin allows the TMPR3911/12 to be the master CHI sync source. As an

input, this pin allows an external peripheral to be the master CHI sync source and the

TMPR3911/12 CHI Module will slave to this external sync.

CHICLK:

INPUT/OUTPUT

This pin is the CHI clock signal. This pin is available for use in one of two modes. As an output,

this pin allows the TMPR3911/12 to be the master CHI clock source. As an input, this pin allows

an external peripheral to be the master CHI clock source and the TMPR3911/12 CHI Module will

slave to this external clock.

CHIDOUT:

OUTPUT

This pin is the CHI serial data output signal.

CHIDIN:

INPUT

This pin is the CHI serial data input signal.

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