TMPR3911 datasheet(176/462 Pages) TOSHIBA

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Chapter 7 CHI Module

7-2

7.2

Interface Requirements

7.2.1

Frame Structure and Serial Timing

Each CHI frame (nominally 8 kHz rate) is time-division-multiplexed into several timeslots or

channels. The total number of timeslots per frame is programmable, with a maximum of 64 timeslots

allowed, and the number of timeslots is also restricted to an even number. Each timeslot is 8 bits,

although 16-bit or 32-bit channels can be supported by accessing adjacent timeslots.

The TMPR3911/12 CHI Module supports a master or slave mode for both the clock (CHICLK) and

sync (CHIFS). For the master mode, the TMPR3911/12 contains programmable dividers for generating

the clock and/or sync signal, synchronously dividing down from the main core clock (CLK). For the

slave mode, TMPR3911/12 accepts external clock and/or sync signals and utilizes “digital-PLL” type

circuitry to stayed “locked” to the external source.

The CHI Module supports the following programmable features which allow support for various

clock and sync timing formats:

•

1x versus 2x clock modes for CHICLK (2x clock mode uses two CHICLK periods per data

bit)

•

MSB-first versus LSB-first serial formats for transmit and receive

•

rising versus falling edge (polarity) used for frame sync triggering

•

CHIFS signal can be sampled on either rising or falling edge of CHICLK

•

CHIDIN receive data can be sampled on either rising or falling edge of CHICLK

•

CHIDOUT transmit data can be pushed on either rising or falling edge of CHICLK

•

CHIDIN receive data can have programmable bit offset (timeslot 0 offset from CHIFS)

•

CHIDOUT transmit data can have programmable bit offset (timeslot 0 offset from CHIFS)

•

CHIDOUT transmit data (tri-state) output buffer enable is dynamically asserted for only

active timeslots; for sleep mode CHIDOUT is always tri-stated

•

for CHIFS master mode, the CHIFS pulse width and polarity is programmable

The TMPR3911/12 CHI Module allows for a programmable bit offset for both CHIDIN and

CHIDOUT, which is related to the number of clock cycles between the start of timeslot 0 and CHIFS.

This flexibility allows the TMPR3911/12 CHI Module to support a wide variety of interface clock and

sync timing formats. The control bits for controlling the CHIDIN bit offset are CHIRXBOFF[3:0],

while the control bits for controlling the CHIDOUT bit offset are CHITXBOFF[3:0].

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