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WM8991 Datasheet(PDF) 83 Page - Wolfson Microelectronics plc |
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WM8991 Datasheet(HTML) 83 Page - Wolfson Microelectronics plc |
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83 / 174 page ![]() Pre-Production WM8991 w PP, May 2008, Rev 3.1 83 GPIO CONTROL REGISTERS Table 45 shows how the dual-function GPIO pins are configured to operate in their different modes. Note that the order of precedence described earlier applies. Register field AIF_SEL selects the function of GPIO3, GPIO4 and GPIO5 between Audio Interface 2 and GPIO functions. Register field ALRCGPIO1 enables the GPIO functionality on GPIO1. Register field MCLK_SRC enables the GPIO functionality on GPIO2. Register field ALRCGPIO6 enables the inverted ADCLRC output on GPIO6. Register bit AIF_TRIS, when set, takes precedence over AIF_SEL, ALRCGPIO1, MCLK_SRC and ALRCBGPIO6 and tri-states all GPIO pins. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R7 (07h) 15 MCLK_SRC 0b MCLK Source Select 0 = MCLK pin 1 = GPIO2/MCLK2 pin R8 (08h) 13 AIF_SEL 0b Audio Interface Select 0 = Audio interface 1 1 = Audio interface 2 (GPIO3/BCLK2, GPIO4/DACLRC2, GPIO5/DACDAT2) 15 ALRCGPIO1 0b ADCLRC/GPIO1 Pin Function Select 0 = ADCLRC 1 = GPIO1 (ADCLRC connected to DACLRC internally) 14 ALRCBGPIO6 0b GPIO6/ADCLRCB Pin Function Select 0 = GPIO6 1 = Inverted ADCLRC clock output R9 (09h) 13 AIF_TRIS 0b Audio Interface and GPIO Tristate 0 = Audio interface and GPIO pins operate normally 1 = Tristate all audio interface and GPIO pins Table 45 GPIO and GPI Pin Function Select The GPIO pins are also controlled by the register fields described in Table 46. Note the order of precedence described earlier applies. Pull-up and pull-down resistors may be enabled on any of GPIO1 to GPIO6. If enabled, these settings take precedence over all other GPIO selections for that pin. Note that, by default, the pull- down resistors on GPIO2, GPIO3, GPIO4, GPIO5 and GPIO6 are enabled. When the GPIO pins are used as inputs, de-bounce and interrupt masking may be controlled on all GPIO pins (including GPI7 and GPI8) using GPIOn_DEB_ENA and GPIOn_IRQ_ENA bits as shown in Table 47. For each of GPIO1 to GPIO6, the register field GPIOn_SEL is used to select the pin functions of the individual GPIO pins as shown in Table 47. Note that this control has the lowest precedence and is only effective when GPIOn_PU, GPIOn_PD, AIF_TRIS, AIFSEL, MCLK_SRC, ALRCGPIO1 and ALRCBGPIO6 are set to allow GPIO functionality on that GPIO pin. |
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