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WM8991 Datasheet(PDF) 31 Page - Wolfson Microelectronics plc |
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WM8991 Datasheet(HTML) 31 Page - Wolfson Microelectronics plc |
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31 / 174 page ![]() Pre-Production WM8991 w PP, May 2008, Rev 3.1 31 AUDIO INTERFACE TIMING – SLAVE MODE Figure 6 Digital Audio Data Timing – Slave Mode Test Conditions DCVDD=1.8V, DBVDD=AVDD=3.3, SPKVDD=5V, DGND=AGND=SPKGND=0V, TA=+25 oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Data Timing Information BCLK (or BCLK2) cycle time tBCY 50 ns BCLK (or BCLK2) pulse width high tBCH 20 ns BCLK (or BCLK2) pulse width low tBCL 20 ns ADCLRC/ DACLRC (or DACLRC2) set-up time to BCLK (or BCLK2) rising edge tLRSU 20 ns ADCLRC/ DACLRC (or DACLRC2) hold time from BCLK (or BCLK2) rising edge tLRH 10 ns DACDAT (or DACDAT2) hold time from BCLK (or BCLK2) rising edge tDH 10 ns ADCDAT propagation delay from BCLK falling edge tDD 20 ns DACDAT (or DACDAT2) set-up time to BCLK (or BCLK2) rising edge tDS 20 ns ADCLRC to ADCLRCB delay tDLRCB 20 ns Note: BCLK (or BCLK2) period should always be greater than or equal to MCLK (or MCLK2) period. |
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