LAN9313 datasheet(113/398 Pages) SMSC

113 / 398 page

Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

113

Revision 1.2 (04-08-08)

DATASHEET

8.2.4

EEPROM Loader

The EEPROM Loader interfaces to the I2C/Microwire EEPROM controller, the PHYs, and to the system

CSRs (via the Register Access MUX). All system CSRs are accessible to the EEPROM Loader.

The EEPROM Loader runs upon a pin reset (nRST), power-on reset (POR), digital reset

(DIGITAL_RST bit in the Reset Control Register (RESET_CTL)), or upon the issuance of a RELOAD

command via the EEPROM Command Register (E2P_CMD). Refer to Section 4.2, "Resets," on

page 41 for additional information on the LAN9313/LAN9313i resets.

The EEPROM contents must be loaded in a specific format for use with the EEPROM Loader. An

overview of the EEPROM content format is shown in Table 8.7. Each section of EEPROM contents is

discussed in detail in the following sections.

8.2.4.1

EEPROM Loader Operation

Upon a pin reset (nRST), power-on reset (POR), digital reset (DIGITAL_RST bit in the Reset Control

While the EEPROM Loader is active, the READY bit of the Hardware Configuration Register

(HW_CFG) is cleared and no writes to the LAN9313/LAN9313i should be attempted. The operational

flow of the EEPROM Loader can be seen in Figure 8.14.

Table 8.7 EEPROM Contents Format Overview

EEPROM ADDRESS

DESCRIPTION

VALUE

EEPROM Valid Flag

A5h

MAC Address Low Word [7:0]

1st Byte on the Network

MAC Address Low Word [15:8]

2nd Byte on the Network

MAC Address Low Word [23:16]

3rd Byte on the Network

MAC Address Low Word [31:24]

4th Byte on the Network

MAC Address High Word [7:0]

5th Byte on the Network

MAC Address High Word [15:8]

6th Byte on the Network

Configuration Strap Values Valid Flag

A5h

8 - 11

Configuration Strap Values

See Table 8.8

Burst Sequence Valid Flag

A5h

Number of Bursts

See Section 8.2.4.5,

"Register Data"

14 and above

Burst Data

See Section 8.2.4.5,

"Register Data"

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