LAN9313 datasheet(115/398 Pages) SMSC

115 / 398 page

Three Port 10/100 Managed Ethernet Switch with MII

Datasheet

SMSC LAN9313/LAN9313i

115

Revision 1.2 (04-08-08)

DATASHEET

8.2.4.2

EEPROM Valid Flag

Following the release of nRST, POR, DIGITAL_RST, or a RELOAD command, the EEPROM Loader

starts by reading the first byte of data from the EEPROM. If the value of A5h is not read from the first

byte, the EEPROM Loader will load the current configuration strap values into the PHY registers (see

Section 8.2.4.4.1) and then terminate, clearing the EPC_BUSY bit in the EEPROM Command Register

(E2P_CMD). Otherwise, the EEPROM Loader will continue reading sequential bytes from the

EEPROM.

8.2.4.3

MAC Address

The next six bytes in the EEPROM, after the EEPROM Valid Flag, are written into the Switch Fabric

MAC Address High Register (SWITCH_MAC_ADDRH) and Switch Fabric MAC Address Low Register

(SWITCH_MAC_ADDRL). The EEPROM bytes are written into the MAC address registers in the order

specified in Table 8.7.

8.2.4.4

Soft-Straps

The 7th byte of data to be read from the EEPROM is the Configuration Strap Values Valid Flag. If this

byte has a value of A5h, the next 4 bytes of data (8-11) are written into the configuration strap registers

per the assignments detailed in Table 8.8. If the flag byte is not A5h, these next 4 bytes are skipped

(they are still read to maintain the data burst, but are discarded). However, the current configuration

strap values are still loaded into the PHY registers (see Section 8.2.4.4.1). Refer to Section 4.2.4,

"Configuration Straps," on page 45 for more information on the LAN9313/LAN9313i configuration

straps.

8.2.4.4.1

PHY REGISTERS SYNCHRONIZATION

Some PHY register defaults are based on configuration straps. In order to maintain consistency

between the updated configuration strap registers and the PHY registers, the Port x PHY Auto-

Negotiation Advertisement Register (PHY_AN_ADV_x), Port x PHY Special Modes Register

(PHY_SPECIAL_MODES_x), and Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) are

written when the EEPROM Loader is run.

The Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) is written with the new

defaults as detailed in Section 13.2.2.5, "Port x PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x)," on page 239.

The Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x) is written with the new defaults

as detailed in Section 13.2.2.9, "Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)," on

page 246.

The Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x) is written with the new defaults

as detailed in Section 13.2.2.1, "Port x PHY Basic Control Register (PHY_BASIC_CONTROL_x)," on

page 233. Additionally, the Restart Auto-negotiation bit is set in this register. This re-runs the Auto-

negotiation using the new default values of the Port x PHY Auto-Negotiation Advertisement Register

(PHY_AN_ADV_x) register to determine the new Auto-negotiation results.

Table 8.8 EEPROM Configuration Bits

BYTE/BIT

765

321

Byte 8

BP_EN_

strap_1

FD_FC_

strap_1

manual_

FC_strap_1

manual_mdix

_strap_1

auto_mdix_

strap_1

speed_

strap_1

duplex_

strap_1

autoneg_

strap_1

Byte 9

BP_EN_

strap_2

FD_FC_

strap_2

manual_

FC_strap_2

manual_mdix

_strap_2

auto_mdix_

strap_2

speed_

strap_2

duplex_

strap_2

autoneg_

strap_2

Byte 10

LED_fun_strap[1:0]

BP_EN_

strap_mii

FD_FC_

strap_mii

manual_FC

_strap_mii

speed_

strap_mii

duplex_pol_

strap_mii

SQE_test_

disable_strap

_mii

Byte 11

LED_en_strap[7:0]

LAN9313 Datasheet(PDF) 115 Page - SMSC Corporation

LAN9313 Datasheet(HTML) 115 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL